Dell S6000–ON - Page 18

B-Row
Parameter
Description
Bit Number(s) This can be either a single bit number or a range starting with the highest bit number (for example, 7 or 7:3).
Name The name of the bit.
Access The access type of the bit; the same as the register denition.
Default Value The default value of the bits.
The following describes the I-row conguration le tree output.
I-Row Parameter Description
I The identier row descriptor.
Value The value of the collection of bits.
Meaning The meaning of the collection of bits.
Example of the pltool Conguration File Output
# ./pltool
Programable Logic Tool
Syntax: ./pltool <option>
-h := show this help
test := test using the test config file
list := list devices and registers
read [b|h|w] device offset [length] := read the specified register
write [b|h|w] device offset data [length] := write at the specified register
Example of the pltool Conguration File Tree Output
# C - CHIP (Master | Slave - Cpld or FPGA), Address, Name, Access
# R - Register, Offset, Mask, Name, RW , Default Val
# B - Bit(s), bitnum(s), Name, RW, Default Val
# I - Information on the bits
=====
C | CPLD | 0x31 | System CPLD | i2c | 0 | 0x00 | 0xf
R | 0x00 | 8 | 0xFF | Board Revision Reg | RO | 0x4A | 1 | 0x0
B | 7:4 | Board Stage | RO | 0x0
B | 3:0 | CPLD Revision | RO | 0x0
R | 0x01 | 8 | 0xFF | Software Reset Reg | RW | 0xFF | 0 | 0x0
B | 7 | Reserved | RW | 0x1
B | 6 | CFast Card Pres | RO | 0x1
B | 5 | CPU HRSTn | RW | 0x1
B | 4 | Super IO RST | RW | 0x1
B | 3 | PE_SATA_RST | RW | 0x1
B | 2 | PE_USB_RST | RW | 0x1
B | 1 | FORCE_RST | RW | 0x1
B | 0 | CPU_RST | RW | 0x1
=====
C | CPLD | 0x32 | Master CPLD | i2c | 0 | 0x01 | 0xf
R | 0x01 | 8 | 0xFF | Board Revision Reg | RW | 0x4C | 1 | 0x0
B | 7:4 | Board Stage | RO | 0x0
I | 4 | P2B-P2C Stage
I | 3 | P2A Stage
I | 2 | P1 Stage
I | 1 | P0 Stage
I | 0 | Testing Code
B | 3:0 | CPLD Revision | RW | 0x0
R | 0x02 | 8 | 0xFF | Power Enable Reg 1/2 | RO | 0x0 | 0 | 0x0
18
ONIE diagnostics