Epson PX-8 - Page 275

REV.-A
Pin No.
Signal Name
In/Out Function
--
20
10RO Tri-state output: During MI cycle
(Input/Output active low
Occurs when the CPU acknowledges a mas-
Request)
kable
interrupt, the external device to put
the interrupt response vector on the data
bus.
Other than during MI cycle
Indicates
that the I/O device number
required for this I/O read/write is output on
the address bus.
-
21 RD Tri-state output:
A signal which indicates that the data
(Read)
active
low bus is in the input state. Memory or I/O
device puts data on the data bus in synchron-
ization with this signal.
-
22 WR
Tri-state: This signal indicates that the data bus is in
(Write)
active
low
the output state. The data to the I/O device
or memory is put on the data bus in synch-
ronization with this signal.
-
28 RF
Output: This signal indicates, during MI cycle, that
(Refresh)
active low the dynamic RAM refresh address is output
onto the lower seven bit lines of the address
bus. Dynamic RAM reads
the refresh address
using
the MREO signal which is output toge-
ther with the RFSH signal.
--
18 HALT
Output:
This signal indicates that CPU has HAL Ted
(Halt State)
active
low as the result of a HALT instruction execution.
---
The INT, NMI, or RESET signal is required to
leave the HAL T state.
CPU repeats dynamic RAM refresh byexecu-
ting a NOP instruction, even while in the
HALTed state.
--
24 WAIT
Input: CPU remains in the WAIT state while this
(Wait)
active low
signal is active. A low speed memory or I/O
device can be directly connected to CPU by
using
this signal.
No memory refresh is performed during the
WAIT state.
7-4