REV.-A
Pin
No.
Signal Name
In/Out
Function
--
16
INTR Input:
An
interrupt request signal.
When
this
(Interrupt Request)
active
low
signal becomes active,
CPU
enters the inter-
rupt processing program after the current
instruction has been executed.
--
17
NMI
Input-negative: A non-maskable interrupt request signal.
(Non Maskable
edge triggered
When
this signal becomes active,
CPU
Interrupt)
jumps
to
address
0066(16)
after the current
instruction has been executed, regardless
of
whether
interrupt is enabled
or
not.
-
The NMI signal has a
priority
over the INT
signal.
-
26
RS
Input:
Resets
CPU
when active.
(Reset)
active
low
--
25
BURO Input:
When
active,
this
signal causes
CPU
to
force
(Bus Request)
active
low
the address bus
(AO-15),
data bus (00-7), and
tri-
state system control terminals (MREO,
IORO,
-
--
RD,
and WD) in the high impedance state,
freeing the external buses
for
another
device.
--
The BUSRO signal has
priority
over the NMI
signal.
--
23
BUAK
Output:
When
active,
this
signal indicates
that
CPU
(Bus
active
low
has forced the address bus, data bus, and tri-
Acknowledge)
state system control terminals in the high
impedance state.
6
ClK
Input
A
0/+5V
single-phase clock signal
(Clock)
7-5
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