Epson PX-8 - Page 293

REV.-A
(3) Timer and baud rate generator
An 2.4576 MHz clock supplied from the outside is divided into a basic clock of 614.4 KHz
(1.6276 ,usee) which operates the free running counter (FRC). FRC is a counter of 16 bits; the low-
order, 8 bit output of the FRC Cover is also used for the RS-232C transmit/ receive clock.
L:OO(R)
[H: 01 (R)]
TolSR
Clock
(614.4 kHz)
Data bus
I
I
OVF}
I
-
'7
ICR(H)
FRC(H) ck
Data bus
~/
I
ICR(L)
,---
I
FRC(L) ck
I
OO(W)
Fig. 7-8
r---
...
....
RXC
0
~
u
OJ
a;
CJ)
~
TXC
}
"-
~
~
SWBCD
...
,/
control register
(selects baud rate)
....
....
'i'
Barcode data
When reading the content of FRC, it is necessary to latch the content to ICR (Input Capture Regis-
ter) by reading address OOH. Because the counter consists of 16 bits, address OOH (low-order 8
bits) and OIH (high-order 8 bits) must be read separately.
Bits 1 and 2, set to the control register, combined with input data cause a trigger signal from
BRDT; this signal allows data going to ICR from FRC to be latched.
7-22