Epson PX-8 - Page 292

REV.-A
(2) Interrupt Controller
Fig.
7-7 shows six kinds of interrupt input, two of which are used for internal timer interrupt.
Priority and
vector addresses are assigned to each interrupt signal as shown in the table below.
Prior-
ity
Low
High
Signal
Name
--
INT5
INT4
INT3
--
INT2
INT1
--
INTO
INT 0
1
2
5
Table 7-7 Priority and Vector Addresses
Description
Interrupt vector
Corresponding Corresponding
D76 5 4 3 2 1 0
mask IER (04) status ISR (04)
(INTEXT) External pin: request from 11111010
IER5
ISR5
external expansion board
(OVF) Inside:
FRC overflow 1 111 1000 IER4 ISR4
(lCF) Inside:
ICR bar code trigger
11110110 IER3
ISR3
(lNT6303) External pin: request from
11110100 IER2
ISR2
6303
(lNT82C51) External pin: request
11110010 IER1
ISR1
from 82C51
(lNT7508) External pin: request from 11110000 IERO ISRO
7508
Address 04 (W)
0
Interrupt acknowledge
A
INT4 INT3
register
(I ER)
...
(OF)
I'r
It
~ \
, ,
r--
....
Interrupt priority
f--
c.
...
:::l ....
/L--
.... 0
encoder
f--
........
0) U
Y--
.... 0)
E>
::
Address 04 (R)
~
Interrupt service
A
~
register (lSR)
D
Data bus
Fig. 7-7
This interrupt controller controls each interrupt acknowledge and mask operation at bit setting for
IER. When an interrupt occurs, a vector address is output on the data bus.
7-21