REV.-A
* The detailed voltage waveform at the anode
of
D6,
shown
below, illustrates an oscillation
which
occurs during charge/discharge
from/to
the inductance L3.
----
-------
~
Damping oscillation I I
I
I
I
IE
~I
Discharge from L3 (Oscillation)
Fig.
2-22
Details
of
L3
Discharge
and
Charge
Cycle
2.2.5.3
RS-232C
Regulator
This regulator is also a DC-DC converter,
which
is enabled only when the RS-232C
or
the serial
interface is used. The circuit includes a control feature
which
prevents its
output
voltage
from being used
for
data transmission during a certain period
of
the rising time until the voltage is
sufficiently stable
to
be used
for
the RS-232C levels.
IC
4C performs
this
control function .
• Circuit Operation
IC
4C initially outputs a high signal at pin
26
(SWRS) and a
low
signal
at
pin
27
(INHRS).
The SWRS signal is inverted by
IC
12D
and fed
to
the base
of
the transistor Q8, turning
it
on.
This causes the battery voltage (VB, +5V)
to
be
output
at the collector
of
the transistor. The
INHRS signal is inverted high by
12D
and then input
to
the base transistor Q18,
cutting
the
transistor off. Q17 is also
cut
off, leaving the transmission line (TXD) floating.
A pulse signal
of
approximately
35
kHz, generated by a
CR
oscillator circuit, is supplied
to
pin 9
of
IC
14D
through R45, C29, and R46. The inverted
output
is fed
to
the base
of
transis-
tor
Q31,
switching
it
on and off. This causes transistor Q
17
to
also
start
switching, thus re-
peating a discharge/charge from
or
to
the inductance L2. This discharge and charge voltage is
half-wave rectified
by
the diode D2, and the positive
output
voltage is filtered by capacitor
C13
to
produce a
DC
voltage
of
+8V.
-8V
is generated at the negative pole
of
capacitor
C14 by the negative component charge
to
capacitor C15 and a negative voltage
swing
at
the anode
of
diode D3 due
to
the charge.
Fig.
2-23
shows
the
timing
relationship among the voltages discussed above.
2-27
To Next Page
Loading...
