REV.-A
2.3.3.3
Slave
CPU
Interrupt
INTR is the only interrupt request signal
to
the slave
CPU
6303;
the NMI signal is
not
used. The
slave
CPU
interrupt is discussed
in
the
following:
Interrupt
control
As
shown
in Fig.
2-43,
the interrupt request signal is generated in
SE01320
and fed
to
the slave
CPU
via GAH40S. This signal is used when the main
CPU
sends a command
to
the slave
CPU
via
the
POIR
register in
SE01320
and is reset when the slave
CPU
reads the
CSR
register in
SE01320.
SED1320
r------------,
GAH40S
Data \
~_i_p
e
o
~
7;
PDIR
PDOR
Main
CPU
AO
zao
'.,
L
_____
I!
__
.;:.
V
AD
\
.
~~
1'\0~7/
C.
PRD
SINT
:::l~
SINT
...
III
IROO
...
ell
PWR
CSR
-----
~E
----
I~
E
1f2
I~
PCS
*
PDIR:
Parallel Data
~~
Input register
GAH40M
*
PDOR:
Parallel Data
E
AS
R/W
INTR
I-
Output register
IR
6303
IW
t---
*
CSR:
Control Status
CSOE
register
Fig.
2-43
Slave
CPU
Interrupt
Control
Block
Diagram
The INTR signal is generated in
SE01320
when the main
CPU
initiates a command,
which
is in
turn fed
to
GAH40S. The signal then interrupts the slave
CPU
under an interrupt mask control by
the slave
CPU
(the interrupt is disabled by
bit
0
of
6303
address
0028
- enabled when the bit is
1).
When interrupted, the slave
CPU
fetches the command
by
reading address
0027.
Slave
CPU
6303
basic
clock
signal
waveforms
(Top) EXTAL:
,-------------------,
Measured
at
130,
pin 3
(Center)
E:
Measured at
130,
pin
40
(Bottom) AS:
Measured at
130,
pin
39
2-47
5V
5V
>500n5
G
'\Mf\MMf\MM[
G
G ____
MMI·II!!!/IJ~.
~;t..n---...li~!!IIIMliI!!!1~~t..Lr\-----1WN!~~!!tIn.L~YL-
5V
5V
Fig.
2-44
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