6 
3 
0 
3 
G 
A 
H 
4 
0 
S 
S 
E 
D 
1 
3 
2 
0 
I 
GAH 
40S 
Address 
OOOD 
OOOE 
OOOF 
0010 
0011 
0012 
0013 
0014 
0020 
0021 
0022 
0023 
0024 
0025 
0026 
0027 
0028 
Read/ 
Function 
Write 
Input Capture register (up-
per 8 bits) 
Input Capture register 
(lower 8 bits) 
Control/status register 
Baudrate/Mode Control 
register 
TX and 
RX 
control/status 
register 
Receive data register 
Transmit data register 
RAM control register 
Counter (upper byte) 
R 
input 
Counter reset 
W 
Counter (lower byte) 
R 
Command register 
W 
P-ROM address (upper 8 
byte) 
W 
P-ROM address (lower 8 
W 
byte) 
P-ROM read data  R 
Controller instruction re-
W 
gister 
Controller data buffer  R 
Controller data buffer 
W 
Controller status register 
R 
Port data output register 
(data) 
W 
Port data input register  R 
Port data output register 
W 
(command) 
Interrupt enable register 
W 
REV.-A 
Bit 
7 
6 
5  4  3  2  1 
0 
Bit15 
Bit 
14 
Bit 
13 
Bit 
12 
Bit 
11 
Bit 
10 
Bit 
9 
Bit 
8 
Bit 
7 
Bit 
6 
Bit5 
Bit 
4 
Bit 
3 
Bit 
2 
Bit 
1 
Bit 
0 
FLAG 
IRQ 
OSS 
LATCH 
enable 
-
enable 
- -
-
Clock control  Baudrate control 
-
-
- -
RDRF 
ORFE 
TDRE 
RIE 
RE 
TIE  TE 
WU 
MSB 
LSB 
MSB 
LSB 
~tand-b'r 
RAM 
power 
enable 
- - - - -
-
CNTR 
Microcassette 
tape 
drive 
counter 
data 
Count 
-
-
Bit 
1 2  I 
Bit 
11 
Bit 
10 
Bit 
9 
Bit 
8 
i 
-
-
- - -
- -
-
Microcassette 
tape 
counter 
data 
Bit 7 
Bit 
6 
Bit 
5 
Bit 
4 
Bit 
3 
Bit 
2 
Bit 
1  BitO 
STOP 
--
SW 
FAST 
-
MTC 
MTB 
MTA 
SWPR 
CNT 
MCT 
Upper 
P-ROM 
address 
bits 
Bit 15  I 
Bit 
14 
I 
Bit 
13 
I 
Bit 
121 
Bit 
11  I 
Bit 
10 
I 
Bit 
9 
I 
Bit 
8 
Upper 
P-ROM 
address 
bits 
Bit 7 
Bit 
6 
Bit 
5 
Bit 
4 
Bit 
3 
Bit 
2 
Bit 
1 
BitO 
MSB 
LSB 
SED 
1320 
• 
6303 
2-46