Epson PX-8 - Page 69

REV.-A
Fig. 2-42 illustrates the vector address operation.
* Vector address - program counter
6303
Memory
Vector Address
I
XX:xxl
I
I I
{~
I
I pel
* The CPU stores the contents of the location addressed
by the
vector address in the program counter.
Fig. 2-42 Vector Address Operation
2.3.3.2 Internal Registers and External Memories
Tabel 2-8 lists the internal registers and external memory locations whitch are used as various
control addresses.
Table 2-8 Internal Registers and External Momory Locations
Read/
Bit
Address Function
Write
7 6 5 4
3
2 1 0
0000
I/O port 1 data direction
I/O Control For Address 0002
register
0001
I/O port 2 data direction
I/O control for address 0003
register
6
Speaker
Speaker
SERIAL SERIAL ,uMCT
,uMCT ,uMCT
0002 I/O port 1 port address power
POUT PIN HSW
,uMCTWE
ERAH
HMT
supply
output
0003
I/O port 2 port address
SERIAL SERIAL
,uMCTWD PRO
3
- - -
PTX PRX
-
0004
I/O port 3 data direction
I/O control for address 0006
register
0
0005
I/O port 4 data direction I/O control for address 0007
register
0006
I/O port 3 port address
Address (lower 8 bits)/data bus
3
0007
I/O port 4 port address
Address bus (upper 8 bits)
0008
Timer control/status re-
gister
0009
Counter (upper 8 bits)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
OOOA
Counter (lower 8 bits)
Bit 7 Bit 6 Bit 5
Bit4 Bit 3 Bit 2 Bit 1 Bit 0
OOOB
Output compare register
Bit
15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
(upper 8 bits)
OOOC
Output compare register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
BitO
(lower 8 bits)
2-45