Espressif Systems ESP32-S3 - Flash and PSRAM; In-Package Flash and PSRAM

Chapter 3. Schematic Checklist
Table 2: Description of Timing Parameters for Power-up and Reset
Parameter Description Minimum (µs)
t
STBL
Time reserved for the power rails to stabilize before the CHIP_PU
pin is pulled high to activate the chip
50
t
RST
Time reserved for CHIP_PU to stay below V
IL_nRST
to reset the
chip
50
Attention:
• CHIP_PU must not be left 󰝙oating.
• To ensure the correct power-up and reset timing, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 μF. However, speci󰝘c
parameters should be adjusted based on the characteristics of the actual power supply and the power-up
and reset timing of the chip.
• If the user application has one of the following scenarios:
– Slow power rise or fall, such as during battery charging.
– Frequent power on/o󰝗 operations.
– Unstable power supply, such as in photovoltaic power generation.
Then, the RC circuit itself may not meet the timing requirements, resulting in the chip being
unable to boot correctly. In this case, additional designs need to be added, such as:
– Adding an external reset chip or a watchdog chip, typically with a threshold of around 3.0
V.
– Implementing reset functionality through a button or the main controller.
3.3 Flash and PSRAM
ESP32-S3 requires in-package or o󰝗-package 󰝙ash to store application 󰝘rmware and data. In-package PSRAM or
o󰝗-package RAM is optional.
3.3.1 In-Package Flash and PSRAM
The tables list the pin-to-pin mapping between the chip and in-package 󰝙ash/PSRAM. Please note that the following
chip pins can connect at most one 󰝙ash and one PSRAM. That is to say, when there is only 󰝙ash in the package, the
pin occupied by 󰝙ash can only connect PSRAM and cannot be used for other functions; when there is only PSRAM,
the pin occupied by PSRAM can only connect 󰝙ash; when there are both 󰝙ash and PSRAM, the pin occupied cannot
connect any more 󰝙ash or PSRAM.
Table 3: Pin-to-Pin Mapping Between Chip and In-Package Quad SPI
Flash
ESP32-S3FN8/ESP32-S3FH4R2 In-Package Flash (Quad SPI)
SPICLK CLK
SPICS0 CS#
SPID DI
SPIQ DO
SPIWP WP#
SPIHD HOLD#
Espressif Systems 13
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