Chapter 4. PCB Layout Design
Fig. 18: ESP32-S3 Waterproof and Proximity Sensing Design
Solution: Add a 10 μF lter capacitor to the branch of the power trace (the branch powering the chip’s analog
power pin). The 10 μF capacitor should be as close to the analog power pin as possible for small and stable voltage
ripples.
4.11.2 2. When ESP32-S3 sends data packages, the voltage ripple is small, but RF TX
performance is poor.
Analysis: The RF TX performance can be aected not only by voltage ripples, but also by the crystal itself. Poor
quality and big frequency osets of the crystal decrease the RF TX performance. The crystal clock may be corrupted
by other interfering signals, such as high-speed output or input signals. In addition, high-frequency signal traces,
such as the SDIO traces and UART traces under the crystal, could also result in the malfunction of the crystal.
Besides, sensitive components or radiating components, such as inductors and antennas, may also decrease the RF
performance.
Solution: This problem is caused by improper layout for the crystal and can be solved by re-layout. Please refer to
Section Crystal for details.
4.11.3 3. When ESP32-S3 sends data packages, the power value is much higher or lower
than the target power value, and the EVM is relatively poor.
Analysis: The disparity between the tested value and the target value may be due to signal reection caused by
the impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance
mismatch will aect the working state of the internal PA, making the PA prematurely access the saturated region in
an abnormal way. The EVM becomes poor as the signal distortion happens.
Solution: Match the antenna’s impedance with the π-type circuit on the RF trace, so that the impedance of the
antenna as seen from the RF pin matches closely with that of the chip. This reduces reections to the minimum.
Espressif Systems 37
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