Espressif Systems ESP32-S3 - ADC; SDIO; USB

Chapter 3. Schematic Checklist
3.9 ADC
Please add a 0.1 μF 󰝘lter capacitor between ESP pins and ground when using the ADC function to improve accuracy.
ADC1 is recommended for use.
The calibrated ADC results after hardware calibration and software calibration are shown in the list below. For higher
accuracy, you may implement your own calibration methods.
• When ATTEN=0 and the e󰝗ective measurement range is 0 ~ 850 mV, the total error is ±5 mV.
• When ATTEN=1 and the e󰝗ective measurement range is 0 ~ 1100 mV, esp32c6=, the total error is ±6 mV.
• When ATTEN=2 and the e󰝗ective measurement range is 0 ~ 1600 mV, the total error is ±10 mV.
• When ATTEN=3 and the e󰝗ective measurement range is 0 ~ 2900 mV, the total error is ±50 mV.
3.10 SDIO
ESP32-S3 only has one SD/MMC Host controller, which cannot be used as a slave device.
The SDIO interface can be con󰝘gured to any free GPIO by software. Please add pull-up resistors to the SDIO GPIO
pins, and it is recommended to reserve a series resistor on each trace.
3.11 USB
ESP32-S3 has a full-speed USB On-The-Go (OTG) peripheral with integrated transceivers. The USB peripheral is
compliant with the USB 2.0 speci󰝘cation.
ESP32-S3 integrates a USB Serial/JTAG controller that supports USB 2.0 full-speed device.
GPIO19 and GPIO20 can be used as D- and D + of USB respectively. It is recommended to populate zero-ohm series
resistors between the mentioned pins and the USB connector. Also, reserve a footprint for a capacitor to ground on
each trace. Note that both components should be placed close to the chip.
Note that USB_D+ will have level output, so please add a pull-up resistor to determine the initial high-level output
voltage.
ESP32-S3 also supports download functions and log message printing via USB. For details please refer to Section
Download Guidelines.
When USB-OTG Download Boot mode is enabled, the chip initializes the IO pad connected to the external PHY in
ROM when starts up. The status of each IO pad after initialization is as follows.
Table 11: IO Pad Status After Chip Initialization in the USB-OTG Down-
load Boot Mode
IO Pad Input/Output Mode Level Status
VP (MTMS) INPUT –
VM (MTDI) INPUT –
RCV (GPIO21) INPUT –
OEN (MTDO) OUTPUT HIGH
VPO (MTCK) OUTPUT LOW
VMO(GPIO38) OUTPUT LOW
If the USB-OTG Download Boot mode is not needed, it is suggested to disable the USB-OTG Download Boot mode
by setting the eFuse bit EFUSE_DIS_USB_OTG_DOWNLOAD_MODE to avoid IO pad state change.
4
GPIO19 and GPIO20 pins both have two high-level glitches during chip power-up, each lasting for about 60 µs. The total duration for the
glitches and the delay are 3.2 ms and 2 ms respectively for GPIO19 and GPIO20.
Espressif Systems 22
Submit Document Feedback
Release master