Espressif Systems ESP32-S3 - UART; Strapping Pins

Chapter 3. Schematic Checklist
Connect the two ends of the matching circuit to the network analyzer, and test its signal re󰝙ection parameter S11
and transmission parameter S21. Adjust the values of the components in the circuit until S11 and S21 meet the
requirements. If your PCB design of the chip strictly follows the PCB design stated in Chapter PCB Layout Design,
you can refer to the value ranges in Table Recommended Value Ranges for Components to debug the matching circuit.
Table 6: Recommended Value Ranges for Components
Reference Desig-
nator
Recommended Value Range Serial No.
C11 1.2 ~ 1.8 pF GRM0335C1H1RXBA01D
L2 2.4 ~ 3.0 nH LQP03TN2NXB02D
C12 1.8 ~ 1.2 pF GRM0335C1H1RXBA01D
If the components are in the 0201 SMD package size, please use a stub in the PCB design of the RF matching circuit
near the chip.
If the usage or production environment is sensitive to electrostatic discharge, it is recommended to reserve ESD
protection devices near the antenna.
Note: If RF function is not required, then the RF pin can be left 󰝙oating.
3.6 UART
It is recommended to connect a 499 Ω series resistor to the U0TXD line to suppress the 80 MHz harmonics.
Usually, UART0 is used as the serial port for download and log printing. For instructions on download over UART0,
please refer to Section Download Guidelines.
Other UART interfaces can be used as serial ports for communication, which could be mapped to any available
GPIO by software con󰝘gurations. For these interfaces, it is also recommended to add a series resistor to the TX line
to suppress harmonics.
When using the AT 󰝘rmware, please note that the UART GPIO is already con󰝘gured (refer to AT Firmware Down-
load). It is recommended to use the default con󰝘guration.
3.7 Strapping Pins
At each startup or reset, a chip requires some initial con󰝘guration parameters, such as in which boot mode to load
the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work as normal
function pins.
All the information about strapping pins is covered in ESP32-S3 Series Datasheet > Section Strapping Pins. In this
document, we will mainly cover the strapping pins related to boot mode.
After chip reset is released, the combination of GPIO0 and GPIO46 controls the boot mode. See Table Boot Mode
Control.
Table 7: Boot Mode Control
Boot Mode GPIO0 GPIO46
Default Con󰝘g 1 (Pull-up) 0 (Pull-down)
SPI Boot (default) 1 Any value
Joint Download Boot
1
0 0
Invalid combination
2
0 1
1
Joint Download Boot mode supports the following download methods:
• USB Download Boot:
Espressif Systems 18
Submit Document Feedback
Release master