Chapter 4. PCB Layout Design
• Place the zero-ohm series resistors on the SPI lines close to the chip.
• Route the SPI traces on the inner layer (e.g., the third layer) whenever possible, and add ground copper and
ground vias around the clock and data traces of SPI separately.
• Place the 0.1 μF capacitor to ground at the VDD_SPI close to corresponding ash and PSRAM power pins.
• Octal SPI traces should have matching lengths.
Figure ESP32-S3 Quad SPI Flash Layout shows the quad SPI ash layout.
Fig. 12: ESP32-S3 Quad SPI Flash Layout
Figure ESP32-S3 Octal SPI Flash Layout shows the octal SPI ash layout.
Fig. 13: ESP32-S3 Octal SPI Flash Layout
4.7 UART
Figure ESP32-S3 UART Layout shows the UART layout.
Espressif Systems 33
Submit Document Feedback
Release master
To Next Page
Loading...
