Chapter 3. Schematic Checklist
Signals applied to the strapping pins should have specic setup time and hold time. For more information, see Figure
Setup and Hold Times for Strapping Pins and Table Description of Timing Parameters for Strapping Pins.
Fig. 12: Setup and Hold Times for Strapping Pins
Table 8: Description of Timing Parameters for Strapping Pins
Parameter Description Minimum (ms)
t
SU
Time reserved for the power rails to stabilize before the chip enable
pin (CHIP_PU) is pulled high to activate the chip.
0
t
H
Time reserved for the chip to read the strapping pin values after
CHIP_PU is already high and before these pins start operating as
regular IO pins.
3
Attention: Do not add high-value capacitors at GPIO0, otherwise, the chip may not boot successfully.
3.8 GPIO
The pins of ESP32-S3 can be congured via IO MUX or GPIO matrix. IO MUX provides the default pin congura-
tions, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more information about
IO MUX and GPIO matrix, please refer to ESP32-S3 Technical Reference Manual > Chapter IO MUX and GPIO
Matrix.
Some peripheral signals have already been routed to certain GPIO pins, while some can be routed to any available
GPIO pins. For details, please refer to ESP32-S3 Series Datasheet > Section Peripheral Pin Congurations.
When using GPIOs, please:
• Pay attention to the states of strapping pins during power-up.
• Pay attention to the default congurations of the GPIOs after reset. The default congurations can be found
in Table IO MUX Pin Functions. It is recommended to add a pull-up or pull-down resistor to pins in the
– USB-Serial-JTAG Download Boot
– USB-OTG Download Boot
• UART Download Boot
2
This combination triggers unexpected behavior and should be avoided.
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