8845A/8846A
Programmers Manual
26
Table 7. Description of Bits in the Status Byte Register
Bit No. Name True (Set to 1) Condition
0 Not used Always set to 0.
1 Not used Always set to 0.
2 Not used Always set to 0.
3 Questionable Data One or more of the enabled events in the
Questionable Data Event Register have occurred.
To determine which Questionable Data events have
occurred, send the Meter STAT:QUES:EVEN? to
read the Questionable Data Event Register.
4 Message Available (MAV) Data is available in the output buffer. Bit set to 1
when response to query placed in output buffer. Bit
cleared (set to 0) when output terminator sent to
host.
5 Standard Event Status (ESB) One or more of the enabled events in the Event
Status Register have occurred. To determine which
events have occurred, send the Meter *ESR? to
read the Event Status Register.
6 Master Summary Status
†
(MSS) Set to 1 if any enabled bit in the STB (MSS) register
is set to 1, otherwise set to 0. Status of MSS bit
returned by *STB? query command.
Request Service (RQS) Set to 1 if service requested
from front panel, or MSS set to 1. Status of bit
returned by serial poll, which clears RQS.
7 Not Used.
† As read by *STB? command. If the Status Byte Register is read by a serial poll, bit 6 is returned as RQS.
Service Request Enable Register
The SRE Register is an 8-bit register that enables or disables (i.e., masks) corresponding
summary messages in the Status Byte Register.
The Meter may be programmed to make a service request on errors, questionable data, or
when output is available. Conditions that trigger a service request are specified by writing
a binary weighted value to the SRE Register, using the *SRE command.
EXAMPLE EXPLANATION
*SRE 16 Enables the generation of an SRQ when bit 4 (Measurement
Available) in the Status Byte Register is set to 1. 16 is the decimal
equivalent of 00010000 binary. This means that bit 4 in SRE
Register (that corresponds to the Measurement Available bit in the
Status Byte Register) is 1, and all other bits are 0.
EXAMPLE EXPLANATION
*SRE 48 Enables the generation of an SRQ when bits 4 or 5 (Measurement
Available or Standard Event) in the Status Byte Register are set to 1.
The binary equivalent of 48 is 00110000, indicating that bits 4 and 5
are set to 1.
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