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1
CHAPTER OVERVIE
W
This chapter describes the supervison functions.
This chapter contains the following sections:
Chapter Over
view
277
Curr
ent Differential Supervision
278
Voltage Transformer Supervision
284
Current Transformer Supervision
289
Trip Circuit Supervision
293
P54A/B/C/E
Chapter 13 - Super
vision
P54xMED-TM-EN-1
277
302
304
Table of Contents
Default Chapter
3
Table of Contents
3
Chapter 1 Introduction
27
Circuit Breaker Fail Logic - Part
28
Rear Serial Port
28
Chapter Overview
29
Trip Circuit Supervision Scheme
29
Cip
29
Foreword
30
Target Audience
30
Typographical Conventions
30
Cip
30
Nomenclature
31
Compliance
31
Cip
31
Product Scope
32
Ordering Options
32
Cip
32
Features and Functions
33
Current Differential Protection Functions
33
Protection Functions
33
Control Functions
33
Measurement Functions
34
Communication Functions
34
Logic Diagrams
35
Figure 1: Key to Logic Diagrams
36
Functional Overview
37
Figure 2: Functional Overview
37
Chapter 2 Safety Information
39
Chapter Overview
41
Health and Safety
42
Symbols
43
Installation, Commissioning and Servicing
44
Lifting Hazards
44
Electrical Hazards
44
UL/CSA/CUL Requirements
45
Fusing Requirements
45
Equipment Connections
46
Protection Class 1 Equipment Requirements
46
Pre-Energisation Checklist
47
Peripheral Circuitry
47
Upgrading/Servicing
48
Decommissioning and Disposal
49
Regulatory Compliance
50
EMC Compliance: 2014/30/EU
50
LVD Compliance: 2014/35/EU
50
R&TTE Compliance: 2014/53/EU
50
UL/CUL Compliance
50
ATEX Compliance: 2014/34/EU
50
Chapter 3 Hardware Design
53
Chapter Overview
55
Hardware Architecture
56
Coprocessor Hardware Architecture
56
Figure 3: Hardware Architecture
56
Figure 4: Coprocessor Hardware Architecture
57
Mechanical Implementation
58
Housing Variants
58
Figure 5: Exploded View of IED
58
List of Boards
59
Front Panel
61
Front Panel Compartments
61
Figure 6: Front Panel (60TE)
61
Keypad
62
Front Serial Port (SK1)
62
Front Parallel Port (SK2)
63
Fixed Function Leds
63
Function Keys
63
Programable Leds
64
Rear Panel
65
Figure 7: Rear View of Populated Case
65
Figure 8: Terminal Block Types
66
Boards and Modules
67
Pcbs
67
Subassemblies
67
Figure 9: Rear Connection to Terminal Block
67
Main Processor Board
68
Figure 10: Main Processor Board
68
Power Supply Board
69
Figure 11: Power Supply Board
69
Figure 12: Power Supply Assembly
70
Watchdog
71
Figure 13: Power Supply Terminals
71
Rear Serial Port
72
Figure 14: Watchdog Contact Terminals
72
Input Module - 1 Transformer Board
73
Figure 15: Rear Serial Port Terminals
73
Figure 16: Input Module - 1 Transformer Board
73
Input Module Circuit Description
74
Figure 17: Input Module Schematic
74
Transformer Board
75
Figure 18: Transformer Board
75
Input Board
76
Figure 19: Input Board
76
Standard Output Relay Board
77
Figure 20: Standard Output Relay Board - 8 Contacts
77
IRIG-B Board
78
Figure 21: IRIG-B Board
78
Fibre Optic Board
79
Figure 22: Fibre Optic Board
79
Rear Communication Board
80
Ethernet Board
80
Figure 23: Rear Communication Board
80
Figure 24: Ethernet Board
80
Redundant Ethernet Board
82
Figure 25: Redundant Ethernet Board
82
Coprocessor Board
84
Current Differential Inputs
84
Coprocessor Board with 1PPS Input
84
Figure 26: Fully Populated Coprocessor Board
84
Chapter 4 Software Design
87
Chapter Overview
89
Sofware Design Overview
90
Figure 27: Software Architecture
90
System Level Software
91
Real Time Operating System
91
System Services Software
91
Self-Diagnostic Software
91
Startup Self-Testing
91
System Boot
91
System Level Software Initialisation
92
Platform Software Initialisation and Monitoring
92
Continuous Self-Testing
92
Platform Software
94
Record Logging
94
Settings Database
94
Interfaces
94
Protection and Control Functions
95
Acquisition of Samples
95
Frequency Tracking
95
Direct Use of Sample Values
95
System Level Software Initialisation
95
Fourier Signal Processing
96
Programmable Scheme Logic
97
Event Recording
97
Figure 28: Frequency Response (Indicative Only)
97
Disturbance Recorder
98
Fault Locator
98
Function Key Interface
98
Chapter 5 Configuration
99
Chapter Overview
101
Settings Application Software
102
Using the HMI Panel
103
Navigating the HMI Panel
104
Getting Started
104
Figure 29: Navigating the HMI
104
Default Display
105
Default Display Navigation
106
Figure 30: Default Display Navigation
106
Password Entry
107
Processing Alarms and Records
107
Menu Structure
108
Changing the Settings
109
Direct Access (the Hotkey Menu)
110
Setting Group Selection Using Hotkeys
110
Control Inputs
110
Circuit Breaker Control
111
Function Keys
111
Line Parameters
113
Tripping Mode
113
CB Trip Conversion Logic Diagram
113
Figure 31: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
113
Residual Compensation
114
Mutual Compensation
114
Date and Time Configuration
116
Using an SNTP Signal
116
Using an IRIG-B Signal
116
Using an IEEE 1588 PTP Signal
116
Without a Timing Source Signal
117
Time Zone Compensation
117
Daylight Saving Time Compensation
118
Settings Group Selection
119
Chapter 6 Current Differential Protection
121
Chapter Overview
123
Current Differential Protection Principle
124
Numerical Current Differential Protection
124
Multi-Ended Line Differential Protection
125
Basic Principles and Algorithm Design for Multi-Ended Differential Protection
125
Fault Discrimination
125
Differential Characteristics
126
Figure 32: Sample Multi-Ended System
126
Figure 33: Current Differential Discriminative Criterion
127
Basic Algorithm
128
Features of Multi-Ended Line Differential
128
Algorithm Overview
128
Communication Requirements
129
Figure 34: Overall Scheme Designed for Multi-Ended Differential Protection
129
Charging Current Compensation
130
Figure 35: Two-Ended Transmission Line
130
Synchronisation of Current Signals
132
Time Alignment Using Ping-Pong Technique
132
Figure 36: Ping-Pong Measurement for Alignment of Current Signals
132
Remote Terminal Time Alignment
133
Time Delay Interpolation
134
Figure 37: Snapshot of Available Data for Processing at each Terminal
134
CT Saturation
135
Figure 38: CT Saturation Technique
135
Figure 39: Original Current Waveforms
136
Figure 40: Ipos and Ineg Current Waveforms
137
Figure 41: Internal External Fault Binary
137
CT Compensation
138
Figure 42: CT Compensation
138
Current Differential Intertripping
139
Figure 43: Permissive Intertripping Example
139
Stub Bus Differential Protection
140
Figure 44: Stub Bus Protection
140
Application Notes
141
Multi-End Current Differential Protection
141
Figure 45: Six Terminal, Four Junction Topology and Ring Structure
141
Figure 46: Six Terminal Ring Structure with Channel Allocation
141
Feeder Topology
142
Configuring the Feeder Topology
142
Figure 47: Six Terminal, Four Junction Topology
142
Line Parameter Data
143
Configuring the Protection Communications
144
Setting up the Phase Differential Characteristic
145
Sensitivity under Heavy Loads
145
Permissive Intertripping
147
CT Ratio Correction Setting Guidelines
147
Feeders with Small Tapped Loads
148
Chapter 7 Autoreclose
149
Chapter Overview
151
Introduction to Autoreclose
152
Autoreclose Implementation
153
Autoreclose Logic Inputs from External Sources
154
Circuit Breaker Healthy Input
154
Inhibit Autoreclose Input
154
Block Autoreclose Input
154
Reset Lockout Input
155
Pole Discrepancy Input
155
External Trip Indication
155
Autoreclose Logic Inputs
155
Trip Initiation Signals
155
Circuit Breaker Status Inputs
155
System Check Signals
155
Autoreclose Logic Outputs
155
Autoreclose Operating Sequence
156
AR Timing Sequence - Transient Fault
156
AR Timing Sequence - Evolving/Permanent Fault
156
Figure 48: Autoreclose Sequence for a Transient Fault
156
AR Timing Sequence - Evolving/Permanent Fault Single-Phase
157
Figure 49: Autoreclose Sequence for an Evolving or Permanent Fault
157
Figure 50: Autoreclose Sequence for an Evolving or Permanent Fault - Single-Phase Operation
157
Autoreclose System Map
158
Figure 51: Key to Logic Diagrams
159
Autoreclose System Map Diagrams
160
Figure 52: Autoreclose System Map - Part 1
160
Figure 53: Autoreclose System Map - Part 2
161
Figure 54: Autoreclose System Map - Part 3
162
Figure 55: Autoreclose System Map - Part 4
163
Figure 56: Autoreclose System Map - Part 5
164
Autoreclose Internal Signals
165
Autoreclose DDB Signals
167
Logic Modules
173
Circuit Breaker Status Monitor
173
CB State Monitor Logic Diagram
174
Figure 57: CB State Monitor Logic Diagram (Module 1)
174
Circuit Breaker Open Logic
175
Circuit Breaker Open Logic Diagram
175
Circuit Breaker in Service Logic
175
Circuit Breaker in Service Logic Diagram
175
Figure 58: Circuit Breaker Open Logic Diagram (Module 3)
175
Figure 59: CB in Service Logic Diagram (Module 4)
175
Autoreclose OK Logic Diagram
176
Autoreclose Enable
176
Autoreclose Enable Logic Diagram
176
Autoreclose Modes
176
Figure 60: Autoreclose OK Logic Diagram (Module 8)
176
Figure 61: Autoreclose Enable Logic Diagram (Module 5)
176
Single-Phase and Three-Phase Autoreclose
177
Autoreclose Modes Enable Logic Diagram
178
AR Force Three-Phase Trip Logic
178
AR Force Three-Phase Trip Logic Diagram
178
Autoreclose Initiation Logic
178
Figure 62: Autoreclose Modes Enable Logic Diagram (Module 9)
178
Figure 63: Force Three-Phase Trip Logic Diagram (Module 10)
178
Autoreclose Initiation Logic Diagram
180
Autoreclose Trip Test Logic Diagram
180
Figure 64: Autoreclose Initiation Logic Diagram (Module 11)
180
Figure 65: Autoreclose Trip Test Logic Diagram (Module 12)
180
AR External Trip Initiation Logic Diagram
181
Figure 66: Autoreclose Initiation by External Trip or Evolving Conditions (Module 13)
181
Protection Reoperation and Evolving Fault Logic Diagram
182
Fault Memory Logic Diagram
182
Autoreclose in Progress
182
Figure 67: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)
182
Figure 68: Fault Memory Logic Diagram (Module 15)
182
Autoreclose in Progress Logic Diagram
183
Sequence Counter
183
Figure 69: Autoreclose in Progress Logic Diagram (Module 16)
183
Autoreclose Sequence Counter Logic Diagram
184
Autoreclose Cycle Selection
184
Single-Phase Autoreclose Cycle Selection Logic Diagram
184
Figure 70: Autoreclose Sequence Counter Logic Diagram (Module 18)
184
Figure 71: Single-Phase Autoreclose Cycle Selection Logic Diagram (Module 19)
184
3-Phase Autoreclose Cycle Selection
185
Dead Time Control
185
Figure 72: Three-Phase Autoreclose Cycle Selection Logic Diagram (Module 21)
185
Dead Time Start Enable Logic Diagram
186
Figure 73: Dead Time Start Enable Logic Diagram (Module 22)
186
1-Phase Dead Time Logic Diagram
187
Figure 74: Single-Phase Dead Time Logic Diagram (Module 24)
187
3-Phase Dead Time Logic Diagram
188
Circuit Breaker Autoclose
188
Figure 75: Three-Phase Dead Time Logic Diagram (Module 25)
188
Circuit Breaker Autoclose Logic Diagram
189
Reclaim Time
189
Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32)
189
Prepare Reclaim Initiation Logic Diagram
190
Reclaim Time Logic Diagram
190
Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34)
190
Figure 78: Reclaim Time Logic Diagram (Module 35)
190
Succesful Autoreclose Signals Logic Diagram
191
Autoreclose Reset Successful Indication Logic Diagram
191
CB Healthy and System Check Timers
191
Figure 79: Successful Autoreclose Signals Logic Diagram (Module 36)
191
Figure 80: Autoreclose Reset Successful Indication Logic Diagram (Module 37)
191
CB Healthy and System Check Timers Logic Diagram
192
Autoreclose Shot Counters
192
Figure 81: Circuit Breaker Healthy and System Check Timers Healthy Logic Diagram (Module 39)
192
Autoreclose Shot Counters Logic Diagram
193
Figure 82: Autoreclose Shot Counters Logic Diagram (Module 41)
193
Circuit Breaker Control
194
CB Control Logic Diagram
194
Figure 83: CB Control Logic Diagram (Module 43)
194
Circuit Breaker Trip Time Monitoring
195
CB Trip Time Monitoring Logic Diagram
195
Autoreclose Lockout
195
Figure 84: Circuit Breaker Trip Time Monitoring Logic Diagram (Module 53)
195
CB Lockout Logic Diagram
196
Figure 85: AR Lockout Logic Diagram (Module 55)
196
Reset Circuit Breaker Lockout
197
Reset CB Lockout Logic Diagram
197
Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
197
Pole Discrepancy
198
Pole Discrepancy Logic Diagram
198
Circuit Breaker Trip Conversion
198
Figure 87: Pole Discrepancy Logic Diagram (Module 62)
198
CB Trip Conversion Logic Diagram
199
Monitor Checks for CB Closure
199
Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
199
Check Synchronisation Monitor for CB Closure
200
Figure 89: Check Synchronisation Monitor for CB Closure (Module 60)
200
Voltage Monitor for CB Closure
201
Synchronisation Checks for CB Closure
201
Figure 90: Voltage Monitor for CB Closure (Module 59)
201
Three-Phase Autoreclose System Check Logic Diagram
203
Figure 91: Three-Phase Autoreclose System Check Logic Diagram (Module 45)
203
CB Manual Close System Check Logic Diagram
204
Figure 92: CB Manual Close System Check Logic Diagram (Module 51)
204
Setting Guidelines
205
De-Ionising Time Guidance
205
Dead Timer Setting Guidelines
205
Example Dead Time Calculation
205
Reclaim Time Setting Guidelines
206
Chapter 8 CB Fail Protection
207
Chapter Overview
209
Circuit Breaker Fail Protection
210
Circuit Breaker Fail Implementation
211
Circuit Breaker Fail Timers
211
Zero Crossing Detection
211
Circuit Breaker Fail Logic
213
Circuit Breaker Fail Logic - Part
213
Figure 96: Circuit Breaker Fail Logic - Part
213
Circuit Breaker Fail Logic - Part
214
Circuit Breaker Fail Logic - Part 3
215
Figure 93: Circuit Breaker Fail Logic - Part
216
Figure 94: Circuit Breaker Fail Logic - Part
216
Figure 95: Circuit Breaker Fail Logic - Part
216
Application Notes
217
Reset Mechanisms for CB Fail Timers
217
Setting Guidelines (CB Fail Timer)
217
Setting Guidelines (Undercurrent)
218
Figure 97: CB Fail Timing
218
Chapter 9 Current Protection Functions
219
Chapter Overview
221
Phase Fault Overcurrent Protection
222
POC Implementation
222
Directional Element
222
POC Logic
224
Figure 98: Phase Overcurrent Protection Logic Diagram
224
Negative Sequence Overcurrent Protection
225
Negative Sequence Overcurrent Protection Implementation
225
Directional Element
225
NPSOC Logic
226
Application Notes
226
Setting Guidelines (Current Threshold)
226
Setting Guidelines (Time Delay)
226
Figure 99: Negative Phase Sequence Overcurrent Protection Logic Diagram
226
Setting Guidelines (Directional Element)
227
Earth Fault Protection
228
Earth Fault Protection Implementation
228
IDG Curve
228
Directional Element
229
Residual Voltage Polarisation
229
Figure 100: IDG Characteristic
229
Negative Sequence Polarisation
230
Earth Fault Protection Logic
231
Application Notes
231
Residual Voltage Polarisation Setting Guidelines
231
Setting Guidelines (Directional Element)
231
Figure 101: Earth Fault Protection Logic Diagram
231
Sensitive Earth Fault Protection
233
SEF Protection Implementation
233
EPATR B Curve
233
Sensitive Earth Fault Protection Logic
234
Figure 102: EPATR B Characteristic Shown for TMS = 1.0
234
Figure 103: Sensitive Earth Fault Protection Logic Diagram
234
Application Notes
235
Insulated Systems
235
Figure 104: Current Distribution in an Insulated System with C Phase Fault
235
Setting Guidelines (Insulated Systems)
236
Figure 105: Phasor Diagrams for Insulated System with C Phase Fault
236
Figure 106: Positioning of Core Balance Current Transformers
237
High Impedance REF
238
High Impedance REF Principle
238
Figure 107: High Impedance REF Principle
238
Figure 108: High Impedance REF Connection
239
Thermal Overload Protection
240
Single Time Constant Characteristic
240
Dual Time Constant Characteristic
240
Thermal Overload Protection Implementation
241
Thermal Overload Protection Logic
241
Application Notes
241
Setting Guidelines for Dual Time Constant Characteristic
241
Figure 109: Thermal Overload Protection Logic Diagram
241
Figure 110: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic
242
Figure 111: Dual Time Constant Thermal Characteristic
242
Setting Guidelines for Single Time Constant Characteristic
243
Broken Conductor Protection
245
Broken Conductor Protection Implementation
245
Broken Conductor Protection Logic
245
Application Notes
245
Setting Guidelines
245
Figure 112: Broken Conductor Logic
245
Chapter 10 Voltage Protection Functions
247
Chapter Overview
249
Undervoltage Protection
250
Undervoltage Protection Implementation
250
Undervoltage Protection Logic
251
Figure 113: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)
251
Application Notes
252
Undervoltage Setting Guidelines
252
Overvoltage Protection
253
Overvoltage Protection Implementation
253
Overvoltage Protection Logic
254
Figure 114: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)
254
Application Notes
255
Overvoltage Setting Guidelines
255
Compensated Overvoltage
256
Residual Overvoltage Protection
257
Residual Overvoltage Protection Implementation
257
Residual Overvoltage Logic
258
Application Notes
258
Calculation for Solidly Earthed Systems
258
Figure 115: Residual Overvoltage Logic
258
Calculation for Impedance Earthed Systems
259
Figure 116: Residual Voltage for a Solidly Earthed System
259
Setting Guidelines
260
Figure 117: Residual Voltage for an Impedance Earthed System
260
Chapter 11 Frequency Protection Functions
261
Chapter Overview
263
Frequency Protection
264
Underfrequency Protection
264
Underfrequency Protection Implementation
264
Underfrequency Protection Logic
265
Application Notes
265
Overfrequency Protection
265
Overfrequency Protection Implementation
265
Figure 118: Underfrequency Logic (Single Stage)
265
Overfrequency Protection Logic
266
Application Notes
266
Figure 119: Overfrequency Logic (Single Stage)
266
Independent R.O.C.O.F Protection
267
Indepenent R.O.C.O.F Protection Implementation
267
Independent R.O.C.O.F Protection Logic
267
Figure 120: Rate of Change of Frequency Logic (Single Stage)
267
Chapter 12 Monitoring and Control
269
Chapter Overview
271
Event Records
272
Event Types
272
Opto-Input Events
273
Contact Events
273
Alarm Events
273
Fault Record Events
274
Maintenance Events
274
Protection Events
274
Figure 121: Fault Recorder Stop Conditions
274
Security Events
275
Platform Events
275
Disturbance Recorder
276
Measurements
277
Measured Quantities
277
Measurement Setup
277
Fault Locator
277
Opto-Input Time Stamping
277
CB Condition Monitoring
278
Broken Current Accumulator
279
CB Trip Counter
279
Figure 122: Broken Current Accumulator Logic Diagram
279
Figure 123: CB Trip Counter Logic Diagram
279
CB Operating Time Accumulator
280
Excessive Fault Frequency Counter
280
Figure 124: Operating Time Accumulator
280
Figure 125: Excessive Fault Frequency Logic Diagram
280
Reset Lockout Alarm
281
Figure 126: Reset Lockout Alarm Logic Diagram
281
CB Condition Monitoring Logic
282
Reset Circuit Breaker Lockout
282
Figure 127: CB Condition Monitoring Logic Diagram
282
Reset CB Lockout Logic Diagram
283
Application Notes
283
Setting the Thresholds for the Total Broken Current
283
Figure 128: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
283
Setting the Thresholds for the Number of Operations
284
Setting the Thresholds for the Operating Time
284
Setting the Thresholds for Excesssive Fault Frequency
284
CB State Monitoring
285
CB State Monitor Logic Diagram
286
Figure 129: CB State Monitor Logic Diagram (Module 1)
286
Circuit Breaker Control
287
CB Control Using the IED Menu
287
CB Control Using the Hotkeys
288
CB Control Using the Function Keys
288
Figure 130: Hotkey Menu Navigation
288
CB Control Using the Opto-Inputs
289
Remote CB Control
289
Figure 131: Default Function Key PSL
289
CB Healthy Check
290
Synchronisation Check
290
CB Control AR Implications
290
Figure 132: Remote Control of Circuit Breaker
290
CB Control Logic Diagram
291
Figure 133: CB Control Logic Diagram (Module 43)
291
Pole Dead Function
292
Pole Dead Logic
292
Figure 134: Pole Dead Logic
292
System Checks
293
System Checks Implementation
293
VT Connections
293
Voltage Monitoring
294
Check Synchronisation
294
Check Syncronisation Vector Diagram
294
Figure 135: Check Synchronisation Vector Diagram
295
Voltage Monitor for CB Closure
296
Figure 136: Voltage Monitor for CB Closure (Module 59)
296
System Checks
296
Check Synchronisation Monitor for CB Closure
297
Figure 137: Check Synchronisation Monitor for CB Closure (Module 60)
297
System Check PSL
298
Application Notes
298
Predictive Closure of Circuit Breaker
298
Voltage and Phase Angle Correction
298
Figure 138: System Check PSL
298
Chapter 13 Supervision
301
Chapter Overview
303
Current Differential Supervision
304
Current Differential Starter Supervision
304
Current Differential Starter Supervision Logic
306
Figure 139: Current Differential Starter Supervision Logic
306
Current Differential Start Logic
307
Switched Communication Path Supervision
307
Figure 140: Current Differential Function Start Logic
307
Communications Asymmetry Supervision
308
Figure 141: Switched Communication Path Supervision
308
Figure 142: Communication Asymmetry Supervision
309
Voltage Transformer Supervision
310
Loss of One or Two Phase Voltages
310
Loss of All Three Phase Voltages
310
Absence of All Three Phase Voltages on Line Energisation
310
VTS Implementation
311
VTS Logic
313
Figure 143: VTS Logic
314
Current Transformer Supervision
315
Differential CTS
315
Differential CTS Logic
316
CTS Implementation
316
Figure 144: Differential CTS
316
Standard CTS Logic
317
CTS Blocking
317
Application Notes
317
Setting Guidelines
317
Figure 145: Standard CTS
317
Differential CTS Setting Guidelines
318
Trip Circuit Supervision
319
Trip Circuit Supervision Scheme
319
Resistor Values
319
Psl for Tcs Scheme 1
320
Trip Circuit Supervision Scheme 2
320
Figure 146: TCS Scheme
321
Figure 147: PSL for TCS Scheme
321
Figure 148: TCS Scheme
321
Figure 149: PSL for TCS Scheme 2
321
Figure 150: TCS Scheme 3
322
Figure 151: PSL for TCS Scheme 3
322
Chapter 14 Digital I/O and PSL Configuration
323
Chapter Overview
325
Configuring Digital Inputs and Outputs
326
Scheme Logic
327
Figure 152: Scheme Logic Interfaces
327
PSL Editor
328
PSL Schemes
328
PSL Scheme Version Control
328
Configuring the Opto-Inputs
329
Assigning the Output Relays
330
Fixed Function Leds
331
Trip LED Logic
331
Figure 153: Trip LED Logic
331
Configuring Programmable Leds
332
Function Keys
334
Control Inputs
335
Chapter 15 Fibre Teleprotection
337
Chapter Overview
339
Fibre Teleprotection Implementation
340
Communication Setup
340
Protection Communications Channel
341
Protection Comms Message Slot Allocation for each Protection Scheme
341
Figure 154: Fibre Teleprotection Connections for a Six-Terminal Scheme
341
Figure 155: Two Terminal Single Channel Scheme
341
Figure 156: Two Terminal Dual Channel Scheme
342
Figure 157: Three Terminal Scheme
342
Figure 158: Four Terminal Scheme
343
Figure 159: Five Terminal Scheme
344
Error Handling for Protection Communications
345
Figure 160: Six Terminal Scheme
345
Fibre Teleprotection Scheme Terminal Addressing
346
Physical Connection
346
Direct Connection
347
Indirect Connection
347
Communications Supervision
348
IM64 Logic
349
Figure 161: IM64 Channel Fail and Scheme Fail Logic
349
Figure 162: IM64 General Alarm Signals Logic
349
Figure 163: IM64 Communications Mode and IEEE C37.94 Alarm Signals
350
Application Notes
351
Scheme Reconfiguration
351
Alarm Management
351
Alarm Logic
351
Two-Ended Scheme Extended Supervision
352
Three-Ended Scheme Extended Supervision
353
Figure 164: IM64 Two-Terminal Scheme Extended Supervision
353
Figure 165: IM64 Three-Terminal Scheme Extended Supervision
353
Chapter 16 Electrical Teleprotection
355
Chapter Overview
357
Introduction
358
Teleprotection Scheme Principles
359
Direct Tripping
359
Permissive Tripping
359
Implementation
360
Configuration
361
Figure 166: Example Assignment of Intermicom Signals Within the PSL
362
Connecting to Electrical Intermicom
363
Short Distance
363
Long Distance
363
Figure 167: Direct Connection
363
Figure 168: Indirect Connection Using Modems
363
Application Notes
364
Chapter 17 Communications
367
Chapter Overview
369
Communication Interfaces
370
Serial Communication
371
EIA(RS)232 Bus
371
EIA(RS)485 Bus
371
EIA(RS)485 Biasing Requirements
372
K-Bus
372
Figure 169: RS485 Biasing Circuit
372
Figure 170: Remote Communication Using K-Bus
373
Standard Ethernet Communication
374
Hot-Standby Ethernet Failover
374
Redundant Ethernet Communication
375
Supported Protocols
375
Parallel Redundancy Protocol
376
Figure 171: IED Attached to Separate Lans
376
High-Availability Seamless Redundancy (HSR)
377
HSR Multicast Topology
377
Figure 172: HSR Multicast Topology
377
HSR Unicast Topology
378
HSR Application in the Substation
378
Figure 173: HSR Unicast Topology
378
Rapid Spanning Tree Protocol
379
Figure 174: HSR Application in the Substation
379
Figure 175: IED Attached to Redundant Ethernet Star or Ring Circuit
379
Self Healing Protocol
380
Figure 176: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities
380
Figure 177: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
380
Dual Homing Protocol
381
Figure 178: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
381
Figure 179: Dual Homing Mechanism
382
Configuring IP Addresses
383
Figure 180: Application of Dual Homing Star at Substation Level
383
Configuring the IED IP Address
384
Configuring the REB IP Address
384
Figure 181: IED and REB IP Address Configuration
384
PRP/HSR Configurator
387
Connecting the IED to a PC
387
Installing the Configurator
388
Starting the Configurator
388
Figure 182: Connection Using (A) an Ethernet Switch and (B) a Media Converter
388
PRP/HSR Device Identification
389
Selecting the Device Mode
389
PRP/HSR IP Address Configuration
389
SNTP IP Address Configuration
389
Check for Connected Equipment
389
PRP Configuration
389
HSR Configuration
390
Filtering Database
390
End of Session
391
RSTP Configurator
391
Connecting the IED to a PC
391
Installing the Configurator
392
Starting the Configurator
392
RSTP Device Identification
392
Figure 183: Connection Using (A) an Ethernet Switch and (B) a Media Converter
392
RSTP IP Address Configuration
393
SNTP IP Address Configuration
393
Check for Connected Equipment
393
RSTP Configuration
393
End of Session
394
Switch Manager
394
Installation
395
Setup
396
Network Setup
396
Bandwidth Used
396
Reset Counters
396
Check for Connected Equipment
396
Mirroring Function
397
Ports On/Off
397
Vlan
397
End of Session
397
Simple Network Management Protocol (SNMP)
398
SNMP Management Information Bases
398
Main Processor MIBS Structure
398
Redundant Ethernet Board MIB Structure
399
Accessing the MIB
403
Main Processor SNMP Configuration
403
Data Protocols
405
Courier
405
Physical Connection and Link Layer
405
Courier Database
406
Settings Categories
406
Setting Changes
406
Event Extraction
406
Disturbance Record Extraction
408
Programmable Scheme Logic Settings
408
Time Synchronisation
408
Courier Configuration
409
Physical Connection and Link Layer
410
Iec 60870-5-103
410
Initialisation
411
Time Synchronisation
411
Spontaneous Events
411
General Interrogation (GI)
411
Cyclic Measurements
411
Commands
411
Test Mode
412
Disturbance Records
412
Command/Monitor Blocking
412
IEC 60870-5-103 Configuration
412
Dnp
413
Physical Connection and Link Layer
414
Object 1 Binary Inputs
414
Object 10 Binary Outputs
414
Object 20 Binary Counters
415
Object 30 Analogue Input
415
Figure 184: Control Input Behaviour
415
Object 40 Analogue Output
416
Object 50 Time Synchronisation
416
DNP3 Device Profile
416
DNP3 Configuration
424
Iec 61850
425
Benefits of IEC 61850
426
IEC 61850 Interoperability
426
The IEC 61850 Data Model
426
IEC 61850 in Micom Ieds
427
Figure 185: Data Model Layers in IEC61850
427
IEC 61850 Data Model Implementation
428
IEC 61850 Communication Services Implementation
428
IEC 61850 Peer-To-Peer (GOOSE) Communications
428
Mapping GOOSE Messages to Virtual Inputs
428
Ethernet Functionality
429
IEC 61850 Configuration
429
Iec 61850 Edition 2
430
Figure 186: Edition 2 System - Backward Compatibility
431
Figure 187: Edition 1 System - Forward Compatibility Issues
431
Figure 188: Example of Standby IED
432
Figure 189: Standby IED Activation Process
433
Read Only Mode
434
Courier Protocol Blocking
434
IEC 61850 Protocol Blocking
435
Read-Only Settings
435
Read-Only DDB Signals
435
Time Synchronisation
436
Demodulated IRIG-B
436
Figure 190: GPS Satellite Timing Signal
436
IRIG-B Implementation
437
Sntp
437
Loss of SNTP Server Signal Alarm
437
IEEE 1588 Precision Time Protocol
437
Accuracy and Delay Calculation
437
PTP Domains
438
Time Synchronsiation Using the Communication Protocols
438
Figure 191: Timing Error Using Ring or Line Topology
438
Chapter 18 Cyber-Security
439
Overview
441
The Need for Cyber-Security
442
Standards
443
NERC Compliance
443
Cip 002
444
Cip 007
445
Ieee 1686-2007
445
Cyber-Security Implementation
447
NERC-Compliant Display
447
Four-Level Access
448
Figure 192: Default Display Navigation
448
Blank Passwords
449
Password Rules
449
Access Level Ddbs
450
Enhanced Password Security
450
Password Strengthening
450
Password Validation
450
Password Blocking
451
Password Recovery
452
Password Encryption
453
Disabling Physical Ports
453
Disabling Logical Ports
453
Security Events Management
454
Logging out
456
Chapter 19 Installation
457
Chapter Overview
459
Handling the Goods
460
Receipt of the Goods
460
Unpacking the Goods
460
Storing the Goods
460
Dismantling the Goods
460
Mounting the Device
461
Flush Panel Mounting
461
Figure 193: Location of Battery Isolation Strip
461
Rack Mounting
462
Figure 194: Rack Mounting of Products
462
Cables and Connectors
464
Terminal Blocks
464
Figure 195: Terminal Block Types
464
Power Supply Connections
465
Earth Connnection
465
Current Transformers
465
Voltage Transformer Connections
466
Watchdog Connections
466
EIA(RS)485 and K-Bus Connections
466
IRIG-B Connection
466
Opto-Input Connections
466
Output Relay Connections
466
Ethernet Metallic Connections
467
Ethernet Fibre Connections
467
RS232 Connection
467
Download/Monitor Port
467
GPS Fibre Connection
467
Fibre Communication Connections
467
Case Dimensions
468
Case Dimensions 40TE
468
Figure 196: 40TE Case Dimensions
468
Case Dimensions 60TE
469
Figure 197: 60TE Case Dimensions
469
Case Dimensions 80TE
470
Figure 198: 80TE Case Dimensions
470
Chapter 20 Commissioning Instructions
471
Chapter Overview
473
General Guidelines
474
Commissioning Test Menu
475
Opto I/P Status Cell (Opto-Input Status)
475
Relay O/P Status Cell (Relay Output Status)
475
Test Port Status Cell
475
Monitor Bit 1 to 8 Cells
475
Test Mode Cell
476
Test Pattern Cell
476
Contact Test Cell
476
Test Leds Cell
476
Test Autoreclose Cell
476
Static Test Mode
477
Loopback Mode
477
IM64 Test Pattern
478
IM64 Test Mode
478
Red and Green LED Status Cells
478
Using a Monitor Port Test Box
478
Commissioning Equipment
479
Recommended Commissioning Equipment
479
Essential Commissioning Equipment
479
Advisory Test Equipment
480
Product Checks
481
Product Checks with the IED De-Energised
481
Visual Inspection
482
Current Transformer Shorting Contacts
482
Insulation
482
External Wiring
482
Watchdog Contacts
483
Power Supply
483
Product Checks with the IED Energised
483
Test LCD
484
Date and Time
484
Test Leds
485
Test Alarm and Out-Of-Service Leds
485
Test Trip LED
485
Test User-Programmable Leds
485
Test Opto-Inputs
485
Test Output Relays
485
Test Serial Communication Port RP1
486
Figure 199: RP1 Physical Connection
486
Test Serial Communication Port RP2
487
Figure 200: Remote Communication Using K-Bus
487
Test Ethernet Communication
488
Secondary Injection Tests
488
Test Current Inputs
488
Test Voltage Inputs
488
Electrical Intermicom Communication Loopback
490
Setting up the Loopback
490
Loopback Test
490
Figure 201: Intermicom Loopback Testing
490
Intermicom Command Bits
491
Intermicom Channel Diagnostics
491
Simulating a Channel Failure
491
Intermicom 64 Communication
492
Checking the Interface
492
Setting up the Loopback
492
Loopback Test
493
Setting Checks
494
Apply Application-Specific Settings
494
Transferring Settings from a Settings File
494
Entering Settings Using the HMI
494
IEC 61850 Edition 2 Testing
496
Using IEC 61850 Edition 2 Test Modes
496
IED Test Mode Behaviour
496
Sampled Value Test Mode Behaviour
496
Simulated Input Behaviour
497
Testing Examples
497
Figure 202: Simulated Input Behaviour
497
Test Procedure for Real Values
498
Test Procedure for Simulated Values - no Plant
498
Figure 203: Test Example 1
498
Test Procedure for Simulated Values - with Plant
499
Figure 204: Test Example 2
499
Contact Test
500
Figure 205: Test Example 3
500
Current Differential Protection
501
Current Differential Bias Characteristic
501
Lower Slope
501
Figure 206: Current Differential Bias Characteristics
501
Upper Slope
502
Current Differential Operation and Contact Assignment
502
Protection Timing Checks
504
Dependency Conditions
504
Overcurrent Check
504
Connecting the Test Circuit
504
Performing the Test
505
Check the Operating Time
505
System Check and Check Synchronism
506
Check Synchronism Pass
506
Check Synchronism Fail
506
Check Trip and Autoreclose Cycle
507
End-To-End Communication Tests
508
Remove Local Loopbacks
508
Restoring Direct Fibre Connections
508
Restoring C37.94 Fibre Connections
509
Remove Remote Loopbacks
509
Verify Communication between Ieds
509
Onload Checks
510
Confirm Voltage Connections
510
Confirm Current Connections
510
Measure Capacitive Charging Current
511
Check Differential Current
511
Check Current Transformer Polarity
511
On-Load Directional Test
511
Final Checks
512
Chapter 21 Maintenance and Troubleshooting
513
Chapter Overview
515
Maintenance
516
Maintenance Checks
516
Alarms
516
Opto-Isolators
516
Output Relays
516
Measurement Accuracy
516
Replacing the Device
517
Repairing the Device
518
Removing the Front Panel
518
Figure 207: Possible Terminal Block Types
518
Replacing Pcbs
519
Replacing the Main Processor Board
519
Replacement of Communications Boards
520
Figure 208: Front Panel Assembly
520
Replacement of the Input Module
521
Replacement of the Power Supply Board
521
Replacement of the I/O Boards
522
Recalibration
522
Changing the Battery
522
Post Modification Tests
523
Battery Disposal
523
Cleaning
523
Troubleshooting
524
Self-Diagnostic Software
524
Power-Up Errors
524
Error Message or Code on Power-Up
524
Out of Service LED on at Power-Up
525
Error Code During Operation
526
Backup Battery
526
Mal-Operation During Testing
526
Failure of Output Contacts
526
Failure of Opto-Inputs
526
Incorrect Analogue Signals
527
Coprocessor Board Failures
527
Signalling Failure Alarm (on Its Own)
527
C Diff Failure Alarm (on Its Own)
527
Signalling Failure and C Diff Failure Alarms Together
527
Incompatible IED
527
Comms Changed
527
IEEE C37.94 Fail
528
PSL Editor Troubleshooting
528
Diagram Reconstruction
528
PSL Version Check
528
Repair and Modification Procedure
528
Chapter 22 Technical Specifications
531
Chapter Overview
533
Interfaces
534
Front Serial Port
534
Download/Monitor Port
534
Rear Serial Port
534
Fibre Rear Serial Port
534
Optional Rear Serial Port (SK5)
535
IRIG-B (Demodulated)
535
IRIG-B (Modulated)
535
Rear Serial Port 2
535
Rear Ethernet Port Copper
536
Rear Ethernet Port Fibre
536
100 Base Fx Receiver Characteristics
536
100 Base Fx Transmitter Characteristics
537
PPS Port
537
Fibre Teleprotection Interface
537
Protection Functions
538
Phase Current Differential Protection
538
Fibre Teleprotection Transfer Times
538
Autoreclose and Check Synychronism
538
Phase Overcurrent Protection
538
Phase Overcurrent Directional Parameters
539
Earth Fault Protection
539
Earth Fault Directional Parameters
539
Sensitive Earth Fault Protection
540
Sensitive Earth Fault Protection Directional Element
540
High Impedance Restricted Earth Fault Protection
540
Negative Sequence Overcurrent Protection
541
NPSOC Directional Parameters
541
Circuit Breaker Fail and Undercurrent Protection
541
Broken Conductor Protection
541
Thermal Overload Protection
541
Monitoring, Control and Supervision
542
Voltage Transformer Supervision
542
Standard Current Transformer Supervision
542
Differential Current Transformer Supervision
542
CB State and Condition Monitoring
542
PSL Timers
543
Measurements and Recording
544
General
544
Disturbance Records
544
Event, Fault and Maintenance Records
544
Fault Locator
544
Ratings
545
AC Measuring Inputs
545
Current Transformer Inputs
545
Voltage Transformer Inputs
545
Auxiliary Supply Voltage
545
Nominal Burden
546
Power Supply Interruption
546
Battery Backup
547
Input / Output Connections
548
Isolated Digital Inputs
548
Nominal Pickup and Reset Thresholds
548
Standard Output Contacts
548
High Break Output Contacts
549
Watchdog Contacts
549
Mechanical Specifications
550
Physical Parameters
550
Enclosure Protection
550
Mechanical Robustness
550
Transit Packaging Performance
550
Type Tests
551
Insulation
551
Creepage Distances and Clearances
551
High Voltage (Dielectric) Withstand
551
Impulse Voltage Withstand Test
551
Environmental Conditions
552
Ambient Temperature Range
552
Temperature Endurance Test
552
Ambient Humidity Range
552
Corrosive Environments
552
Electromagnetic Compatibility
553
Mhz Burst High Frequency Disturbance Test
553
Damped Oscillatory Test
553
Immunity to Electrostatic Discharge
553
Electrical Fast Transient or Burst Requirements
553
Surge Withstand Capability
553
Surge Immunity Test
554
Immunity to Radiated Electromagnetic Energy
554
Radiated Immunity from Digital Communications
554
Radiated Immunity from Digital Radio Telephones
554
Immunity to Conducted Disturbances Induced by Radio Frequency Fields
554
Magnetic Field Immunity
555
Conducted Emissions
555
Radiated Emissions
555
Power Frequency
555
Regulatory Compliance
556
EMC Compliance: 2014/30/EU
556
LVD Compliance: 2014/35/EU
556
R&TTE Compliance: 2014/53/EU
556
UL/CUL Compliance
556
ATEX Compliance: 2014/34/EU
556
Appendix A Ordering Options
559
Appendix B Settings and Signals
561
4
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GE P4A Specifications
General
Brand
GE
Model
P4A
Category
Relays
Language
English
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