Figure 79: Low impedance restricted Earth Fault logic 175
Figure 80: REF 2nd harmonic blocking logic 177
Figure 81: Star winding, resistance earthed 178
Figure 82: Percentage of winding protected 178
Figure 83: Low Impedance REF Scaling Factor 179
Figure 84: Low-Z REF for dual CB application with different phase CT ratios 180
Figure 85: Low-Z REF for dual CB application with same phase CT ratios 181
Figure 86: Hi-Z REF protection for a grounded star winding 184
Figure 87: Hi-Z REF protection for a delta winding 184
Figure 88: Hi-Z REF Protection for autotransformer configuration 185
Figure 89: High Impedance REF for the LV winding 185
Figure 90: High Impedance REF CT requirement 190
Figure 91: IEC 60255 IDMT curves 196
Figure 92: Principle of protection function implementation 199
Figure 93: Magnetising inrush phenomenon 201
Figure 94: Non-directional overcurrent logic diagram 204
Figure 95: Directional overcurrent logic diagram 207
Figure 96: Typical distribution system using parallel transformers 209
Figure 97: Selecting the current threshold setting 210
Figure 98: Modification of current pickup level for voltage controlled overcurrent protection 211
Figure 99: Negative Sequence Overcurrent logic - non-directional operation 212
Figure 100: Negative Phase equence Overcurrent logic - directional operation 213
Figure 101: Non-directional EF logic (single stage) 217
Figure 102: IDG Characteristic 218
Figure 103: Directional EF logic with neutral voltage polarization (single stage) 219
Figure 104: Directional Earth Fault logic with negative phase sequence polarisation (single
stage)
220
Figure 105: Phase overcurrent 2nd harmonic blocking Logic 223
Figure 106: Earth fault 2nd harmonic blocking Logic 223
Figure 107: Circuit Breaker Fail Logic - part 1 231
Figure 108: Circuit Breaker Fail Logic - part 2 232
Figure 109: CB Fail timing 234
Figure 110: Undervoltage - single and three phase tripping mode (single stage) 239
Figure 111: Overvoltage - single and three phase tripping mode (single stage) 242
Figure 112: Residual Overvoltage logic 245
Figure 113: Residual voltage for a solidly earthed system 246
Figure 114: Residual voltage for an impedance earthed system 247
Figure 115: Negative Sequence Overvoltage logic 248
Figure 116: Variable time overfluxing protection characteristic 255
Figure 117: Overfluxing reset characteristic 256
P64x Table of Figures
P64x-TM-EN-1.3 xix