GE P643 - Case Dimensions 80 TE; Figure 168: 80 TE Case Dimensions

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5.3 CASE DIMENSIONS 80TE

413.2

177.00

222.00

407.10

30.00

240.00

INCL. WIRING

157.50 MAX

SIDE VIEW

SECONDARY COVER

(WHEN FITTED)

116.55 142.45

12 OFF HOLES

3.40

168.00

4.50

129.50155.40

408.90

62.00

159.00

74.95

FRONT VIEW

TERMINAL SCREWS : M4 X 7 BRASS CHEESE HEAD SCREWS WITH

LOCK WASHERS PROVIDED.

MOUNTING SCREW : M4 X 12 SEM UNIT STEEL THREAD

FORMING SCREW.

FLUSH MOUNTING PANEL

CUT-OUT DETAIL

E01410

Figure 168: 80TE case dimensions

Chapter 18 - Installation P64x

406 P64x-TM-EN-1.3

Main Page

Default Chapter3
- Table of Contents3
Chapter 1 Introduction25
- Rear Serial Port26
- Figure 137: TCS Scheme26
Chapter Overview27
- Cip27
Foreword28
- Target Audience28
- Typographical Conventions28
- Cip28
- Nomenclature29
- Cip29
Product Scope30
- Product Versions30
- Cip30
- Ordering Options31
- Figure 1: P64X Version Evolution31
Features and Functions32
- Protection Functions32
- Control Functions32
- Measurement Functions33
- Communication Functions33
Compliance34
Functional Overview35
- Figure 2: Functional Overview35
Chapter 2 Safety Information37
Chapter Overview39
Health and Safety40
Symbols41
Installation, Commissioning and Servicing42
- Lifting Hazards42
- Electrical Hazards42
- UL/CSA/CUL Requirements43
- Fusing Requirements43
- Equipment Connections44
- Protection Class 1 Equipment Requirements44
- Pre-Energisation Checklist45
- Peripheral Circuitry45
- Upgrading/Servicing46
Decommissioning and Disposal47
Standards Compliance48
- EMC Compliance: 2004/108/EC48
- Product Safety: 2006/95/EC48
- R&TTE Compliance48
- UL/CUL Compliance48
- ATEX Compliance48
Chapter 3 Hardware Design51
Chapter Overview53
Hardware Architecture54
- Figure 3: Hardware Architecture54
Mechanical Implementation55
- Housing Variants55
- Figure 4: Exploded View of IED55
- List of Boards56
Front Panel58
- Front Panel Compartments58
- Figure 5: Front Panel (60TE)58
- HMI Panel59
- Front Serial Port (SK1)59
- Figure 6: HMI Panel59
- Front Parallel Port (SK2)60
- Fixed Function Leds60
- Function Keys60
- Programable Leds61
Rear Panel62
- Figure 7: Rear View of Populated Case62
- Figure 8: Terminal Block Types63
Boards and Modules64
- Pcbs64
- Subassemblies64
- Figure 9: Rear Connection to Terminal Block64
- Main Processor Board65
- Figure 10: Main Processor Board65
- Power Supply Board66
- Figure 11: Power Supply Board66
- Figure 12: Power Supply Assembly67
- Watchdog68
- Figure 13: Power Supply Terminals68
- Rear Serial Port69
- Figure 14: Watchdog Contact Terminals69
- Input Module - 1 Transformer Board70
- Figure 15: Rear Serial Port Terminals70
- Figure 16: Input Module - 1 Transformer Board70
- Input Module Circuit Description71
- Figure 17: Input Module Schematic71
- Frequency Response72
- Figure 18: Frequency Response72
- Transformer Board73
- Figure 19: Transformer Board73
- Input Board74
- Figure 20: Input Board74
- Standard Output Relay Board75
- Figure 21: Standard Output Relay Board - 8 Contacts75
- IRIG-B Board76
- Figure 22: IRIG-B Board76
- Fibre Optic Board77
- Figure 23: Fibre Optic Board77
- Rear Communication Board78
- Ethernet Board78
- Figure 24: Rear Communication Board78
- Figure 25: Ethernet Board78
- Redundant Ethernet Board80
- Figure 26: Redundant Ethernet Board80
- RTD Board82
- Figure 27: RTD Board82
- CLIO Board83
- Figure 28: RTD Board83
- High Break Output Relay Board85
- Figure 29: High Break Relay Output Board85
- Figure 30: High Break Contact Operation86
Chapter 4 Software Design87
Chapter Overview89
Sofware Design Overview90
- Figure 31: Software Architecture90
System Level Software91
- Real Time Operating System91
- System Services Software91
- Self-Diagnostic Software91
- Startup Self-Testing91
- System Boot91
- System Level Software Initialisation92
- Platform Software Initialisation and Monitoring92
- Continuous Self-Testing92
Platform Software94
- Record Logging94
- Settings Database94
- Interfaces94
Protection and Control Functions95
- Acquisition of Samples95
- Frequency Tracking95
- Direct Use of Sample Values95
- Fourier Signal Processing95
- Programmable Scheme Logic96
- Figure 32: Frequency Response (Indicative Only)96
- Event Recording97
- Disturbance Recorder97
- Fault Locator97
- Function Key Interface97
Chapter 5 Configuration99
Chapter Overview101
Using the HMI Panel102
- Navigating the HMI Panel103
- Getting Started103
- Figure 33: Navigating the HMI103
- Default Display104
- Default Display Navigation105
- Figure 34: Default Display Navigation105
- Password Entry106
- Processing Alarms and Records106
- Menu Structure107
- Changing the Settings108
- Direct Access (the Hotkey Menu)109
- Setting Group Selection Using Hotkeys109
- Control Inputs109
- Function Keys110
Configuring the Data Protocols112
- Courier Configuration112
- DNP3 Configuration113
- DNP3 Configurator114
- MODBUS Configuration116
- IEC 61850 Configuration117
- IEC 61850 Configuration Banks118
- IEC 61850 Network Connectivity118
Date and Time Configuration119
- Time Zone Compensation119
- Daylight Saving Time Compensation119
Phase Rotation120
- CT and VT Reversal120
Chapter 6 Transformer Differential Protection121
Chapter Overview123
Transformer Differential Protection Principles124
- Through Fault Stability124
- Bias Current Compensation124
- Three-Phase Transformer Connection Types125
- Figure 35: Compensation Using Biased Differential Characteristic125
- Figure 36: Transformer Winding Connections - Part 1127
- Phase and Amplitude Compensation128
- Figure 37: Transformer Winding Connections - Part 2128
- Zero Sequence Filtering129
- Magnetising Inrush Restraint129
- Figure 38: Magnetising Inrush Phenomenon129
- Overfluxing Restraint130
- Figure 39: Typical Overflux Current Waveform130
Implementation131
- Defining the Power Transformer131
- Selecting the Current Inputs131
- Phase Correction132
- Ratio Correction132
- CT Parameter Mismatch133
- Figure 40: CT Parameter Mismatch Logic Diagram133
- Setting up Zero Sequence Filtering134
- Tripping Characteristics134
- High-Set Function135
- Circuitry Fail Alarm135
- Figure 41: Transformer Biased Tripping Characteristic135
- Tripping Characteristic Stability136
- Maximum Bias136
- Delayed Bias136
- Transient Bias136
- CT Saturation Technique137
- No Gap Detection Technique137
- External Fault Detection Technique137
- Figure 42: Transient Bias Characteristic137
- Current Transformer Supervision138
- Figure 43: Time to Saturation - External an Fault138
- Circuitry Fail Alarm139
- Figure 44: Effect of CTS Restrain139
- Figure 45: Bias Characteristic with Circuitry Fail Alarm139
- Differential Biased Trip Logic140
- Figure 46: Differential Biased Trip Logic140
Harmonic Blocking141
- 2Nd Harmonic Blocking141
- Figure 47: 2Nd Harmonic Blocking Process141
- 2Nd Harmonic Blocking Logic142
- 5Th Harmonic Blocking Implementation142
- Figure 48: 2Nd Harmonic Blocking Logic142
- 5Th Harmonic Setting Guideline143
- Geomagnetic Disturbances143
- Overall Harmonic Blocking Logic143
- Figure 49: 5Th Harmonic Blocking Process143
- Figure 50: Differential Protection Blocking Mechanisms144
Application Notes145
- Setting Guidelines145
- Example 1: Two-Winding Transformer - no Tap Changer146
- Figure 51: Triple Slope Characteristic146
- Figure 52: P642 Used to Protect a Two Winding Transformer146
- Example 2: Autotransformer with Loaded Delta Winding148
- Figure 53: P645 Used to Protect an Autotransformer with Loaded Delta Winding149
- Example 3: Autotransformer with Unloaded Delta Winding151
- Figure 54: P643 Used to Protect an Autotransformer with Unloaded Delta Winding152
- Figure 55: Unloaded Delta - Current Distribution153
- Setting Guidelines for Short-Interconnected Biased Differential Protection154
- Figure 56: Single Bus Differential Protection Zone155
- Setting Guidelines for Shunt Reactor Biased Differential Protection157
- Figure 57: Busbar Biased Differential Protection157
- Figure 58: Shunt Reactor Single Line Diagram158
- Setting Guidelines for Using Spare CT Inputs159
- Setting Guidelines for Reference Vector Group160
- Figure 59: P643 Using Spare CT Input for Overcurrent Protection160
- Stub Bus Application161
- Stub Bus Implementation161
- Figure 60: Stub Bus Arrangement161
- Stub Bus Scheme162
- Transformer Differential Protection CT Requirements162
- CT Requirements - Transformer Application162
- Figure 61: Stub Bus Scheme Logic162
- CT Requirements - Small Busbar Application163
Chapter 7 Transformer Condition Monitoring165
Chapter Overview167
Thermal Overload Protection168
- Thermal Overload Implementation168
- Figure 62: Transformer Losses168
- Thermal Overload Bias Current169
- The Thermal Model170
- Top Oil Temperature Caculations170
- Hotspot Caculations170
- Thermal State Measurement171
- Application Notes171
- Alstom Recommendations171
- IEEE Recommendations171
- Data Provided by Transformer Manufacturers172
Loss of Life Statistics174
- Loss of Life Implementation174
- Loss of Life Calculations174
- Application Notes176
- LOL Setting Guidelines176
- Example176
Through Fault Monitoring178
- Through Fault Monitoring Implementation178
- Through Fault Monitoring Logic179
- Application Notes179
- TFM Setting Guidelines179
  - Figure 63: Through-Fault Alarm Logic179
  - Through Fault Monitoring179
- Figure 64: P645 Used to Protect an Autotransformer with Loaded Delta Winding180
RTD Protection181
- RTD Protection Implementation181
- Figure 65: Connection for RTD Thermal Probes181
- RTD Logic182
- Application Notes182
- Setting Guidelines for RTD Protection182
- Figure 66: RTD Logic182
CLIO Protection183
- Current Loop Input Implementation183
- Figure 67: Current Loop Input Ranges184
- Current Loop Input Logic185
- CLO Implementation185
- Figure 68: Current Loop Input Logic185
- Figure 69: Current Loop Output Ranges186
- Application Notes187
- CLI Setting Guidelines187
- CLO Setting Guidelines187
Chapter 8 Restricted Earth Fault Protection189
Chapter Overview191
REF Protection Principles192
- Figure 70: REF Protection for Delta Side192
- Figure 71: REF Protection for Star Side192
- Resistance-Earthed Star Windings193
- Solidly-Earthed Star Windings193
- Figure 72: REF Protection for Resistance-Earthed Systems193
- Figure 73: REF Protection for Solidly Earthed System193
- Through Fault Stability194
- Restricted Earth Fault Types194
- Low Impedance REF Principle194
- High Impedance REF Principle195
- Figure 74: Low Impedance REF Connection195
- Figure 75: Three-Slope REF Bias Characteristic195
- Figure 76: High Impedance REF Principle196
- Figure 77: High Impedance REF Connection196
Restricted Earth Fault Protection Implementation197
- Enabling REF Protection197
- Selecting the Current Inputs197
- Low Impedance REF198
- Setting the Bias Characteristic198
- Figure 78: REF Bias Characteristic198
- Delayed Bias199
- Transient Bias199
- Restricted Earth Fault Logic199
- High Impedance REF199
- Figure 79: Low Impedance Restricted Earth Fault Logic199
- High Impedance REF Calculation Principles200
Second Harmonic Blocking201
- REF 2Nd Harmonic Blocking Logic201
- Figure 80: REF 2Nd Harmonic Blocking Logic201
Application Notes202
- Star Winding Resistance Earthed202
- Figure 81: Star Winding, Resistance Earthed202
- Figure 82: Percentage of Winding Protected202
- Low Impedance REF Protection Application203
- Setting Guidelines for Biased Operation203
- Low Impedance REF Scaling Factor203
- Parameter Calculations203
- Figure 83: Low Impedance REF Scaling Factor203
- Dual CB Application with Different Phase CT Ratios204
- Figure 84: Low-Z REF for Dual CB Application with Different Phase CT Ratios204
- Dual CB Application with same Phase CT Ratios205
- CT Requirements - Low Impedance REF205
- Figure 85: Low-Z REF for Dual CB Application with same Phase CT Ratios205
- High Impedance REF Protection Application207
- High Impedance REF Operating Modes207
- Figure 86: Hi-Z REF Protection for a Grounded Star Winding208
- Figure 87: Hi-Z REF Protection for a Delta Winding208
- Setting Guidelines for High Impedance Operation209
- Figure 88: Hi-Z REF Protection for Autotransformer Configuration209
- Figure 89: High Impedance REF for the LV Winding209
- Use of Metrosil Non-Linear Resistors211
- CT Requirements - High Impedance REF213
- Figure 90: High Impedance REF CT Requirement214
Chapter 9 Current Protection Functions215
Chapter Overview217
Overcurrent Protection Principles218
- IDMT Characteristics218
- IEC 60255 IDMT Curves219
- European Standards220
- Figure 91: IEC 60255 IDMT Curves220
- North American Standards222
- Differences between the North American and European Standards223
- Principles of Implementation223
- Figure 92: Principle of Protection Function Implementation223
- Timer Hold Facility224
- Magnetising Inrush Restraint224
- Figure 93: Magnetising Inrush Phenomenon225
Phase Overcurrent Protection226
- Phase Overcurrent Protection for Power Transformers226
- Phase Overcurrent Protection Implementation226
- Selecting the Current Inputs227
- Non-Directional Overcurrent Logic228
- Figure 94: Non-Directional Overcurrent Logic Diagram228
- Directional Element229
- Implementing Directionalisation229
- Directional Overcurrent Logic231
- Application Notes231
- Setting Guidelines231
- Figure 95: Directional Overcurrent Logic Diagram231
- Parallel Feeders233
- Figure 96: Typical Distribution System Using Parallel Transformers233
Voltage Dependent Overcurrent Element234
- Current Setting Threshold Selection234
- VCO Implementation234
- Figure 97: Selecting the Current Threshold Setting234
- Figure 98: Modification of Current Pickup Level for Voltage Controlled Overcurrent Protection235
Negative Sequence Overcurrent Protection236
- NPSOC Protection Implementation236
- Non-Directional NPSOC Logic236
- Figure 99: Negative Sequence Overcurrent Logic - Non-Directional Operation236
- Directional Element237
- Directional NPSOC Logic237
- Figure 100: Negative Phase Equence Overcurrent Logic - Directional Operation237
- Application Notes238
- Setting Guidelines (General)238
- Setting Guidelines (Current Threshold)238
- Setting Guidelines (Time Delay)238
- Setting Guidelines (Directional Element)238
Earth Fault Protection240
- Earth Fault Protection Elements240
- Non-Directional Earth Fault Logic241
- IDG Curve241
- Figure 101: Non-Directional EF Logic (Single Stage)241
- Directional Element242
- Residual Voltage Polarisation242
- Figure 102: IDG Characteristic242
- Negative Sequence Polarisation243
- Figure 103: Directional EF Logic with Neutral Voltage Polarization (Single Stage)243
- Application Notes244
- Setting Guidelines (Non-Directional)244
- Figure 104: Directional Earth Fault Logic with Negative Phase Sequence Polarisation244
- Setting Guidelines (Directional Element)245
Second Harmonic Blocking246
- Second Harmonic Blocking Implementation246
- Second Harmonic Blocking Logic247
- EF Second Harmonic Blocking Logic247
- Application Notes247
- Setting Guidelines247
- Figure 105: Phase Overcurrent 2Nd Harmonic Blocking Logic247
- Figure 106: Earth Fault 2Nd Harmonic Blocking Logic247
Chapter 10 CB Fail Protection249
Chapter Overview251
Circuit Breaker Fail Protection252
Circuit Breaker Fail Implementation253
- Circuit Breaker Fail Timers253
- Zero Crossing Detection254
Circuit Breaker Fail Logic255
- Figure 107: Circuit Breaker Fail Logic - Part 1255
- Figure 108: Circuit Breaker Fail Logic - Part 2256
Application Notes257
- Reset Mechanisms for CB Fail Timers257
- Setting Guidelines (CB Fail Timer)257
- Setting Guidelines (Undercurrent)258
- Figure 109: CB Fail Timing258
Chapter 11 Voltage Protection Functions259
Chapter Overview261
Undervoltage Protection262
- Undervoltage Protection Implementation262
- Undervoltage Protection Logic263
- Figure 110: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)263
- Application Notes264
- Undervoltage Setting Guidelines264
Overvoltage Protection265
- Overvoltage Protection Implementation265
- Overvoltage Protection Logic266
- Application Notes266
- Overvoltage Setting Guidelines266
- Figure 111: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)266
Residual Overvoltage Protection268
- Residual Overvoltage Protection Implementation268
- Residual Overvoltage Logic269
- Application Notes269
- Calculation for Solidly Earthed Systems269
- Figure 112: Residual Overvoltage Logic269
- Calculation for Impedance Earthed Systems270
- Figure 113: Residual Voltage for a Solidly Earthed System270
- Setting Guidelines271
- Figure 114: Residual Voltage for an Impedance Earthed System271
Negative Sequence Overvoltage Protection272
- Negative Sequence Overvoltage Implementation272
- Negative Sequence Overvoltage Logic272
- Application Notes272
- Setting Guidelines272
- Figure 115: Negative Sequence Overvoltage Logic272
Chapter 12 Frequency Protection Functions275
Chapter Overview277
Overfluxing Protection278
- Overfluxing Protection Implementation278
- Time-Delayed Overfluxing Protection279
- Figure 116: Variable Time Overfluxing Protection Characteristic279
- 5Th Harmonic Blocking280
- Overfluxing Protection Logic280
- Figure 117: Overfluxing Reset Characteristic280
- Figure 118: 5Th Harmonic Blocking Time Delay in PSL280
- Application Notes281
- Overfluxing Protection Setting Guidelines281
- Figure 119: Overfluxing Protection Logic281
- Figure 120: Multi-Stage Overfluxing Characteristic282
- Figure 121: Scheme Logic for Multi-Stage Overfluxing Characteristic282
Frequency Protection283
- Underfrequency Protection283
- Underfrequency Protection Implementation283
- Underfrequency Protection Logic283
- Figure 122: Underfrequency Logic (Single Stage)283
- Application Notes284
- Overfrequency Protection284
- Overfrequency Protection Implementation284
- Overfrequency Protection Logic284
- Figure 123: Overfrequency Logic (Single Stage)284
- Application Notes285
Chapter 13 Monitoring and Control287
Chapter Overview289
Event Records290
- Event Types290
- Opto-Input Events291
- Contact Events291
- Alarm Events291
- Fault Record Events295
- Maintenance Events295
- Figure 124: Fault Recorder Stop Conditions295
- Protection Events296
- Security Events296
- Platform Events296
Disturbance Recorder297
Measurements298
- Measured Quantities298
- Measured and Calculated Currents298
- Measured and Calculated Voltages298
- Power and Energy Quantities298
- Demand Values299
- Other Measurements299
- Measurement Setup299
- Opto-Input Time Stamping299
Current Input Exclusion Function300
- Current Input Exclusion Logic300
- Application Notes300
- Current Input Exclusion Example300
- Figure 125: CT Exclusion Logic300
- Figure 126: CT Input Exclusion - 1.5 CB Application301
- Figure 127: CT Input Exclusion - Auxiliary Contact Connection301
Pole Dead Function302
- Pole Dead Function Implementation302
- Pole Dead Logic303
- Figure 128: Pole Dead Logic - P642303
- CB Status Indication304
- Figure 129: Pole Dead Logic - P643 and P645304
- Figure 130: Forcing CB Closed Signals305
Chapter 14 Supervision307
Chapter Overview309
Voltage Transformer Supervision310
- Loss of One or Two Phase Voltages310
- Loss of All Three Phase Voltages310
- Absence of All Three Phase Voltages on Line Energisation310
- VTS Implementation311
- VTS Logic312
- Figure 131: VTS Logic (P642 with 2 Single-Phase Vts)312
- Figure 132: VTS Logic (P643 and P645 with 3-Phase Vts)313
Current Transformer Supervision315
- CTS Implementation315
- Figure 133: CTS Restraint Region Increase315
- CTS Logic316
- Figure 134: CTS Logic Diagram316
- Application Notes317
- Setting Guidelines317
Trip Circuit Supervision318
- Trip Circuit Supervision Scheme318
- Resistor Values318
- Figure 135: TCS Scheme 1318
- Psl for Tcs Scheme 1319
- Trip Circuit Supervision Scheme319
- Figure 136: PSL for TCS Scheme 1319
- Resistor Values320
- Psl for Tcs Scheme 2320
- Trip Circuit Supervision Scheme320
- Figure 138: PSL for TCS Scheme 2320
- Figure 139: TCS Scheme 3320
- Resistor Values321
- Psl for Tcs Scheme 3321
- Figure 140: PSL for TCS Scheme 3321
Chapter 15 Digital I/O and PSL Configuration323
Chapter Overview325
Configuring Digital Inputs and Outputs326
Scheme Logic327
- Figure 141: Scheme Logic Interfaces327
- PSL Editor328
- PSL Schemes328
- PSL Scheme Version Control328
Configuring the Opto-Inputs329
Assigning the Output Relays330
Fixed Function Leds331
- Trip LED Logic331
- Figure 142: Trip LED Logic331
Configuring Programmable Leds332
Function Keys334
Control Inputs335
Chapter 16 Communications337
Chapter Overview339
Communication Interfaces340
Serial Communication341
- EIA(RS)232 Bus341
- EIA(RS)485 Bus341
- EIA(RS)485 Biasing Requirements342
- K-Bus342
- Figure 143: RS485 Biasing Circuit342
- Figure 144: Remote Communication Using K-Bus343
Standard Ethernet Communication344
- Hot-Standby Ethernet Failover344
Redundant Ethernet Communication345
- Supported Protocols345
- Parallel Redundancy Protocol346
- Figure 145: IED Attached to Separate Lans346
- Rapid Spanning Tree Protocol347
- Self Healing Protocol347
- Figure 146: IED Attached to Redundant Ethernet Star or Ring Circuit347
- Figure 147: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities348
- Figure 148: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches348
- Figure 149: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches348
- Dual Homing Protocol349
- Figure 150: Dual Homing Mechanism349
- Redundant Ethernet Configuration350
- Figure 151: Application of Dual Homing Star at Substation Level350
- Figure 152: IED and REB Switch IP Address Configuration351
- Figure 153: DIP Switches for Setting IP Address351
- Setting the NIC IP Address352
- Setting the Switch IP Address352
Data Protocols353
- Courier353
- Physical Connection and Link Layer353
- Courier Database354
- Settings Categories354
- Setting Changes354
- Event Extraction354
- Disturbance Record Extraction356
- Programmable Scheme Logic Settings356
- Time Synchronisation356
- Courier Configuration357
- Physical Connection and Link Layer358
- Iec 60870-5-103358
- Initialisation359
- Time Synchronisation359
- Spontaneous Events359
- General Interrogation (GI)359
- Cyclic Measurements359
- Commands359
- Test Mode360
- Disturbance Records360
- Command/Monitor Blocking360
- IEC 60870-5-103 Configuration360
- Dnp361
- Physical Connection and Link Layer362
- Object 1 Binary Inputs362
- Object 10 Binary Outputs362
- Object 20 Binary Counters363
- Object 30 Analogue Input363
- Figure 154: Control Input Behaviour363
- Object 40 Analogue Output364
- Object 50 Time Synchronisation364
- DNP3 Device Profile364
- DNP3 Configuration372
- Modbus373
- Physical Connection and Link Layer374
- MODBUS Functions374
- Response Codes374
- Register Mapping375
- Event Extraction375
- Disturbance Record Extraction376
- Figure 155: Manual Selection of a Disturbance Record379
- Figure 156: Automatic Selection of Disturbance Record - Method 1380
- Figure 157: Automatic Selection of Disturbance Record - Method 2381
- Figure 158: Configuration File Extraction382
- Figure 159: Data File Extraction383
- Setting Changes384
- Password Protection384
- Protection and Disturbance Recorder Settings384
- Time Synchronisation385
- Power and Energy Measurement Data Formats386
- MODBUS Configuration387
- Iec 61850388
- Benefits of IEC 61850388
- IEC 61850 Interoperability389
- The IEC 61850 Data Model389
- Figure 160: Data Model Layers in IEC61850389
- IEC 61850 in Micom Ieds390
- IEC 61850 Data Model Implementation390
- IEC 61850 Communication Services Implementation390
- IEC 61850 Peer-To-Peer (GOOSE) Communications391
- Mapping GOOSE Messages to Virtual Inputs391
- Ethernet Functionality391
- IEC 61850 Configuration391
Read Only Mode393
- Courier Protocol Blocking393
- IEC 61850 Protocol Blocking394
- Read-Only Settings394
- Read-Only DDB Signals394
Time Synchronisation395
- Demodulated IRIG-B395
- IRIG-B Implementation395
- Figure 161: GPS Satellite Timing Signal395
- Sntp396
- Time Synchronsiation Using the Communication Protocols396
Chapter 17 Cyber-Security397
Overview399
The Need for Cyber-Security400
Standards401
- NERC Compliance401
- Cip 002402
- Cip 007403
- Ieee 1686-2007403
Cyber-Security Implementation405
- NERC-Compliant Display405
- Four-Level Access406
- Figure 162: Default Display Navigation406
- Blank Passwords407
- Password Rules407
- Access Level Ddbs408
- Enhanced Password Security408
- Password Strengthening408
- Password Validation408
- Password Blocking409
- Password Recovery410
- Password Encryption411
- Disabling Physical Ports411
- Disabling Logical Ports411
- Security Events Management412
- Logging out414
Chapter 18 Installation415
Chapter Overview417
Handling the Goods418
- Receipt of the Goods418
- Unpacking the Goods418
- Storing the Goods418
- Dismantling the Goods418
Mounting the Device419
- Flush Panel Mounting419
- Figure 163: Location of Battery Isolation Strip419
- Rack Mounting420
- Figure 164: Rack Mounting of Products420
Cables and Connectors422
- Terminal Blocks422
- Figure 165: Terminal Block Types422
- Power Supply Connections423
- Earth Connnection423
- Current Transformers423
- Voltage Transformer Connections424
- Watchdog Connections424
- EIA(RS)485 and K-Bus Connections424
- IRIG-B Connection424
- Opto-Input Connections424
- Output Relay Connections424
- Ethernet Metallic Connections425
- Ethernet Fibre Connections425
- RS232 Connection425
- Download/Monitor Port425
- GPS Fibre Connection425
- Fibre Communication Connections425
- RTD Connections426
- CLIO Connections427
Case Dimensions428
- Case Dimensions 40TE428
- Figure 166: 40TE Case Dimensions428
- Case Dimensions 60TE429
- Figure 167: 60TE Case Dimensions429
- Case Dimensions 80TE430
- Figure 168: 80TE Case Dimensions430
Chapter 19 Commissioning Instructions431
Chapter Overview433
General Guidelines434
Commissioning Test Menu435
- Opto I/P Status Cell (Opto-Input Status)435
- Relay O/P Status Cell (Relay Output Status)435
- Test Mode Cell435
- Test Pattern Cell436
- Contact Test Cell436
- Test Leds Cell436
- Red and Green LED Status Cells436
- PSL Verificiation436
- Test Port Status Cell436
- Monitor Bit 1 to 8 Cells436
- Using a Monitor Port Test Box437
Commissioning Equipment438
- Recommended Commissioning Equipment438
- Essential Commissioning Equipment438
- Advisory Test Equipment439
Product Checks440
- Product Checks with the IED De-Energised440
- Visual Inspection441
- Current Transformer Shorting Contacts441
- Insulation441
- External Wiring441
- Watchdog Contacts442
- Power Supply442
- Product Checks with the IED Energised442
- Test LCD443
- Date and Time443
- Test Leds444
- Test Alarm and Out-Of-Service Leds444
- Test Trip LED444
- Test User-Programmable Leds444
- Test Opto-Inputs444
- Test Output Relays444
- RTD Inputs445
- Current Loop Outputs445
- Current Loop Inputs445
- Test Serial Communication Port RP1446
- Figure 169: RP1 Physical Connection446
- Test Serial Communication Port RP2447
- Figure 170: Remote Communication Using K-Bus447
- Test Ethernet Communication448
- Secondary Injection Tests448
- Test Current Inputs448
- Test Voltage Inputs449
Setting Checks450
- Apply Application-Specific Settings450
- Transferring Settings from a Settings File450
- Entering Settings Using the HMI450
Checking the Differential Element452
- Using the Omicron Advanced Module452
- Figure 171: Operating Characteristic Diagram453
- Figure 172: Trip Time Test Plane453
- Figure 173: Harmonic Restraint Test Plane454
Protection Timing Checks455
- Bypassing the All Pole Dead Blocking Condition455
- Overcurrent Check455
- Connecting the Test Circuit455
- Performing the Test455
- Check the Operating Time455
Onload Checks457
- Confirm Current Connections457
- Confirm Voltage Connections457
- On-Load Directional Test458
Final Checks459
Chapter 20 Maintenance and Troubleshooting461
Chapter Overview463
Maintenance464
- Maintenance Checks464
- Alarms464
- Opto-Isolators464
- Output Relays464
- Measurement Accuracy464
- Replacing the Device465
- Repairing the Device466
- Removing the Front Panel466
- Figure 174: Possible Terminal Block Types466
- Replacing Pcbs467
- Replacing the Main Processor Board467
- Replacement of Communications Boards468
- Figure 175: Front Panel Assembly468
- Replacement of the Input Module469
- Replacement of the Power Supply Board469
- Replacement of the I/O Boards470
- Recalibration470
- Changing the Battery470
- Post Modification Tests471
- Battery Disposal471
- Cleaning471
Troubleshooting472
- Self-Diagnostic Software472
- Power-Up Errors472
- Error Message or Code on Power-Up472
- Out of Service LED on at Power-Up473
- Error Code During Operation474
- Backup Battery474
- Mal-Operation During Testing474
- Failure of Output Contacts474
- Failure of Opto-Inputs474
- Incorrect Analogue Signals475
- PSL Editor Troubleshooting475
- Diagram Reconstruction475
- PSL Version Check475
Repair and Modification Procedure476
Chapter 21 Technical Specifications477
Chapter Overview479
Interfaces480
- Front Serial Port480
- Download/Monitor Port480
- Rear Serial Port480
- Fibre Rear Serial Port480
- IRIG-B (Demodulated)481
- IRIG-B (Modulated)481
- Rear Ethernet Port Copper481
- Rear Serial Port 2481
- Rear Ethernet Port Fibre482
- 100 Base Fx Receiver Characteristics482
- 100 Base Fx Transmitter Characteristics482
Performance of Transformer Differential Protection and Monitoring Functions483
- Transformer Differential Protection483
- Matching Factors483
- Circuitry Fault Alarm483
- Through Fault Monitoring484
- Thermal Overload484
- Low Impedance Restricted Earth Fault484
- High Impedance Restricted Earth Fault484
Performance of Current Protection Functions485
- Transient Overreach and Overshoot485
- Three-Phase Overcurrent Protection485
- Three-Phase Overcurrent Directional Parameters485
- Voltage Dependent Overcurrent Protection485
- Earth Fault Protection486
- Earth Fault Directional Parameters486
- Negative Sequence Overcurrent Protection486
- NPSOC Directional Parameters486
- Circuit Breaker Fail Protection487
Performance of Voltage Protection Functions488
- Undervoltage Protection (P643/5)488
- Overvoltage Protection488
- Residual Overvoltage Protection (P643/5)488
- Negative Sequence Voltage Protection488
Performance of Frequency Protection Functions489
- Overfrequency Protection489
- Underfrequency Protection489
- Overfluxing Protection489
Performance of Monitoring and Control Functions490
- Voltage Transformer Supervision490
- Current Transformer Supervision490
- Pole Dead Protection490
- PSL Timers491
Measurements and Recording492
- General492
- Disturbance Records492
- Event, Fault and Maintenance Records492
- Current Loop Inputs/Outputs492
Standards Compliance494
- EMC Compliance: 2004/108/EC494
- Product Safety: 2006/95/EC494
- R&TTE Compliance494
- UL/CUL Compliance494
- ATEX Compliance494
- IDMT Standards495
Mechanical Specifications496
- Physical Parameters496
- Enclosure Protection496
- Mechanical Robustness496
- Transit Packaging Performance496
Ratings497
- AC Measuring Inputs497
- Current Transformer Inputs497
- Voltage Transformer Inputs497
Power Supply498
- Auxiliary Supply Voltage498
- Nominal Burden498
- Power Supply Interruption498
- Battery Backup499
Input / Output Connections500
- Isolated Digital Inputs500
- Nominal Pickup and Reset Thresholds500
- Standard Output Contacts500
- High Break Output Contacts501
- Watchdog Contacts501
Environmental Conditions502
- Ambient Temperature Range502
- Temperature Endurance Test502
- Ambient Humidity Range502
- Corrosive Environments502
Type Tests503
- Insulation503
- Creepage Distances and Clearances503
- High Voltage (Dielectric) Withstand503
- Impulse Voltage Withstand Test503
Electromagnetic Compatibility504
- Mhz Burst High Frequency Disturbance Test504
- Damped Oscillatory Test504
- Immunity to Electrostatic Discharge504
- Electrical Fast Transient or Burst Requirements504
- Surge Withstand Capability504
- Surge Immunity Test505
- Immunity to Radiated Electromagnetic Energy505
- Radiated Immunity from Digital Communications505
- Radiated Immunity from Digital Radio Telephones505
- Immunity to Conducted Disturbances Induced by Radio Frequency Fields505
- Magnetic Field Immunity506
- Conducted Emissions506
- Radiated Emissions506
- Power Frequency506
Appendix A Ordering Options507
Appendix B Settings and Signals509
Appendix C Wiring Diagrams515

GE P643 - Case Dimensions 80 TE; Figure 168: 80 TE Case Dimensions

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