Great Scott Gadgets HackRF - 25 LPC4350 SGPIO Experimentation; SGPIO Examples

CHAPTER
TWENTYFIVE
LPC4350 SGPIO EXPERIMENTATION
The NXP LPC43xx microcontrollers have an interesting, programmable serial peripheral called the SGPIO (Serial
GPIO). It consists of a slew of counters and shift registers that can be configured to serialize and deserialize many
channels of data. Channels can be grouped to create multi-bit parallel data streams.
The current HackRF design entails using the SGPIO peripheral to move quadrature baseband receive and transmit data
between the USB interface and the baseband ADC/DAC IC. Because the baseband ADC/DAC IC (MAX5864) uses
DDR signaling, we expect to use a CPLD to convert bus signaling. The CPLD may also help manage bus turnaround
(between transmit and receive modes) or interfacing two narrower but faster interfaces to the LPC43xx to facilitate
full-duplex.
Because the Jellybean board wasn’t completed at the time of these experiments, I used the Diolan LPC-4350-DB1-A
development board. Despite using an LPC4350 in an BGA256 package, the SGPIO peripheral’s signals can be mapped
to many different pins. So reworking code to a new set of SGPIO pins should be a trivial matter of switching the SGU
configuration for the affected pins.
25.1 SGPIO Examples
Some SGPIO peripheral examples can be found in the LPCWare repository. All source I’ve found so far is focused on
generating many I2S interfaces, which is not very similar to HackRF’s needs. But reviewing the code is still valuable
in grasping how the SGPIO peripheral operates.
There are a few common details to setting up the SGPIO peripheral:
// Configure the PLL to generate a reasonable clock. The SGPIO
// will operate with a clock of up to 204MHz (the same as the
// M4 clock.
CGU_SetPLL1(12);
// Set the BASE_PERIPH clock to come from PLL1.
CGU_EnableEntity(CGU_BASE_PERIPH, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_PERIPH);
// Compute and commit clock configuration changes.
CGU_UpdateClock();
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