CHAPTER
TWENTYTHREE
FUTURE HARDWARE MODIFICATIONS
Things to consider for post-Jawbreaker hardware designs:
23.1 Antenna
The PCB antenna on Jawbreaker was included to facilitate beta testing. Future designs likely will not include a PCB
antenna.
SMA connectors will be PCB edge-mounted.
23.2 Baseband
The interfaces between the MAX2837 and MAX5864 have some signals inverted. Theoretically, that’s fine if compen-
sated for in software. However, I’m theorizing that RX/ADC DC offset compensation assumes that both channels have
the same DC polarity. I’ve fixed the inversion in the CPLD. However, a PCB experiment should be conducted to see if
the DC offset is reduced by un-inverting the RX Q channel connections to the MAX5864.
23.3 CPLD
The CPLD could be removed, but some sort of multiplexer would be needed to meet the MAX5864 i/o requirements.
Depending on the particular LPC43xx part used, it might be possible to use the System Control Unit (SCU) for this.
23.4 Clocking
The clock signal from the Si5351C to the LPC43xx’s GP_CLKIN pin may need different passives, but the documen-
tation on that clock input is thin (acceptable peak-to-peak voltage anyone?).
An unpopulated footprint for a 32.768 kHz RTC crystal would be nice. Also break out RTC battery pins to an expansion
header.
85
To Next Page
Loading...