CHAPTER
SEVENTEEN
CLOCKING
HackRF clock signals are generated by the Si5351. The plan so far:
• crystal frequency: 25 MHz (supports 25 or 27 MHz)
• optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division)
• VCO frequency: 800 MHz (supports 600 to 900 MHz)
• MAX2837 clock: 40 MHz
• preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
• A clock at double the MAX5864 rate will be delivered to the CPLD and SGPIO.
• LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work)
Lemondrop+Jellybean Si5351 output mapping:
• CLK0 -> MAX2837
• CLK1 -> MAX5864/CPLD
• CLK2 -> CPLD
• CLK3 -> CPLD
• CLK4 -> LPC4330
• CLK5 -> RFFC5072
• CLK6 -> extra
• CLK7 -> extra
Jawbreaker output mapping:
• CLK0 -> MAX5864/CPLD
• CLK1 -> CPLD
• CLK2 -> SGPIO
• CLK3 -> external clock output
• CLK4 -> RFFC5072
• CLK5 -> MAX2837
• CLK6 -> none
• CLK7 -> LPC4330 (but LPC4330 will start up on its own crystal)
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