bass to
lower
coupler is
"ON".
In each of
these
modes the
"String
Bass" and
the "Mute"
features can be
used.
The
following
descriptions are
step by
step
circuit analyses
of the
Bass
Generator
Board
for the 5
different
modes of
operation.
Refer to Figures 3,
EXAMPLE #1
-
MODE #1
Assuming that pedal #2 (CJ)
is
depressed and the bass
tab is set for
16',
the following
operation occurs:
The
activation pedal H2 (C#),transfers
a logic
1 (ground potential) to J503
pin 2
of the Bass
Generator Board. This logic
1 (grd) passes
through the matrix diode
D6 and
reaches the D7 input of
priority
encoder
IC2 at pin 4. The logic 1 (grd) at
J503
pin 2 also changes the
bass select
data
buss (R) and the
keydown data
buss (S) from a logic
(—14V) to logic 1
(grd).
With a
logic 1 (grd) applied to
the D7
input
of IC2, the EO output
(pin
15)
of
IC2
falls from a logic 1 (grd)
to a logic
(—
14V). This
transition disables IC1.
Also,
at this time,
the Gs output of 1C2
rises from a
logic
(—
14V) to a
logic 1
(grd). The Gs
output is
supplied to the
input of
transistor Ql.
Finally with a
logic 1 (grd)
applied to the
D7 input. IC2
releases
the note select
code of
(1, 1, 1)
from
its
Q2,
Ql and QO
outputs. These
outputs exist on
pins
6,
7,
and
9
respectively.
After the Gs
output of IC2 is
inverted
to a logic
(—14V) by
transistor Ql
,
the
signal
works with the
inverted Gs
output of
IC3 (logic 1 at
transistor Q2's
output) to
form the 2-bit
inhibit/ enable
code.
The 2-bit code
activates two
latches
with ICs 9 and
10. The logic
(—
14V)
at
the output
of transistor
Ql combines
with the
logic 1 (grd) of the
keydown
data
buss {S> at
NAND gate IC10D;
the
logic
(—14V) also travels to
the input
pin 6 of
IC9A
-
one half
of a latch
consisting
of IC9A and
1C9B
.
The logic
1
(grd) and
logic
(—-14V) inputs to
1C10D force a logic
1 output at
pin 11 of
IC10D.
Now, with a logic
(
—14V) applied to
pin 1 of IC9A and a logic 1 applied to pin
6 of IC9B, the latch forces a logic
(—
14V) to pin 4 of IC9B. This logic
(—
14V) travels to the disable input (Dl
pin 15) of data selector IC5.
With
logicO
(—
14V) maintained at the
Dl input of
the ICS, the chip
becomes enabled and,
therefore, available for operation. The
logic
(—
14V) at
IC9B
pin 4 is also
applied
to
IC11A pin 2. At IC11A, the
logic
(—
14V) combines with the
output of IC10B pin 4. To determine the
output level of IC10B pin 4, we must
follow the Gs output of 1C3.
Because priority encoder IC2 receives
no logic 1
(grd) D inputs with the Of
pedal depressed,
its
Gs
output must
maintain a logic
(—14V) level.
Transistor
Q2
inverts this logic
(—14V)
into
a
logic 1 (grd) and applies
that level to pin 9 of IC10C and pin 6 of
IC10B.
The logic 1 (grd) output of Q2
then
combines with
the logic 1 (grd) of the
keydown buss at
IC10C. As a result, the
NAND gate
output pin 10 falls to a logic
(—
14V)
which is transferred to pin 1 of
IC10A. Now, because the input pin 6 of
IC10B is held to logic 1 (grd). and
the
input pin 1 of
1C10A is held to logic
(—
14V), the
iatch forces a logic 1 (grd)
atlClOA
pin 3.
The
logic 1 (grd) at IC10A pin 3
travels to
the disable (D2) input of data
selector
IC4 pin 15. This disables IC4.
Also, the
logic 1 (grd) at pin 3 of ICIOA
combines with logic
(—
14V) from
pin
4 of IC9A at
IC11A. The logic 1 (grd)
and logic
(—14V) inputs of IC11A
force a
logic 1 (grd) at pin 3 of
IC11A,
and this
level reaches the disable (DO)
input
of IC6, disabling IC6.
Thus far,
we have examined how the Gs
outputs of ICs 2 and 3
have formed a
2-
bit
inhibit/enable code that has
enabled IC5 and has inhibited IC4 and
IC6 when the pedal is depressed.
In
order for IC4 to release
the appropriate
bass frequency,
the chip must receive a
3-
bit note
select code at its A, B, and C
inputs.
Therefore, we must return to the
Q2,
Ql and
QO outputs of IC2.
Earlier,
we stated that with
the D7
input
of IC2 held to a logic
1 (grd), the
chip's
Q2,
Ql and QO outputs were al'
logic
1 (grd) levels. These levels are
sent
directly
to the inverting NOR gates
of 1C7. IC7's A, B,
and C sections invert
the
Q2,
Ql and
QO outputs of IC2 to
logic
(
—14V) levels. These levels are
then applied to the latches of ICs 8 and
9. and to NAND gate IC11.
The inverted
Q2
output leaves pin 6 of
IC7A as a logic
(—
14V). This level is
transferred to pin 13 of IC11D as well as
to pin 13 at IC9D. At 1C11D the logic 1
(grd) of the keydown
data buss com-
bines with the logic
(
—
14V)
to force
the NAND gate to release a logic 1 (grd)
to pin 8 of 1C9C. Now, with IC9C and
IC9D receiving logic 1 (grd) and logic
(—
14V) inputs respectively, the pin 11
output of latch IC9C/9D goes to a hi
'
logic I (grd) level. This level is applied
to
the "C" data line of the data
selectors ICs
4,
5, and 6.
The
inverted
Ql
output leaves pin 9 of
IC7B
as a
logic (—14V). Also from pin
9 the
low level travels to pin 5 of 1C11B
as well as
to
pin 1 of IC8A. At IC11B the
logic (—14V) from IC7 pin 9 becomes
"NANDED" with the logic 1 (grd) of
the keydown data buss. The
NAND
process yields a logic 1
(grd)
at
pin
6 of
1C8B. The
combination of logic 1 (grd)
at pin
6 of IC8B and the logic at pin 1
of IC8A makes flip-flop IC8B/8A pro-
vide a logic 1 (grd) to the "B" data line
of data selectors.
Finally, the logic
(—
14V) QO
out,"^
of IC7C pin 10
travels
to
pin 9 of IC11C
and to
pin 13 of IC8D. IC11C NANDS
the logic 1 (grd) of the keydown buss
and the logic
(—14V) output of IC7C.
This holds pin 8 of IC8C to logic I (grd).
Consequently, the flip-flop IC8C/8A
places a logic 1 (grd) level on the "A"
data
line of the data selectors.
At this time data
selectors ICs
4, 5,
and 6
receive logic l's (grd) at their A,
B, and C
inputs. These inputs will be
maintained by the flip-flops
even after
pedal #2
is released (to allow the sustain
in
String Bass).
Only IC5
responds to
the code at
its A, B, and C inputs
because IC4 and 6 are disabled by
the
logic
1 (grd) levels at their D inputs.
The
result of this process is the
transfer™
the Ot bass signal
from the XI data
input of
ICS to the Z signal
output of
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