1 The signal is
available on the Z line
because
the Z output
pins
of
disabled
ICs 4 and 6 are at
high impedances.
The C# square
wave
released by the
data selector is Inverted by
NAND gate
IC12C. This inverted
signal travels to
pin 12 of IC12D as well as to
pin 11 of
1C15. 1C15 divides the C# bass
signal by
2 twice. The resultant signal from the
first
stage of division leaves IC15 at pin
13 and
enters NAND gate IC12A at pin
2;
the signal from the second stage
leaves
IC15 at pin 1 and enters IC12 at
pin 6.
At
this time the highest C#
frequency
(high bass)
is available at IC12D, the
s'—'wd highest
C#
frequency (medium
b.
J)
is
available at IC12A.
and the
lowest
C#
frequency (low
bass) is
available at
1C12B. The NAND gates
of
IC14,
however, will not pass the
low.
medium or high
bass signals unless pins
5,
1, and 13
receive logic 1 (grd)
levels.
To
determine if these inputs exist,
we
must examine the
operation of octave
select circuitry IC13
and transistors
Q5
and Q6.
Because
the Cft pedal is
within the
group of
pedals 1
through
5,
both the
keydown data buss (S)
and the bass
select
data buss (R) are
held at logic l's
(grd)
during pedal
down. IC13D
NANDS
these two logic l's
(grd) levels.
This forces
a logic
(—14V) at pin 11 of
I^~*D.
IC13C then
NANDS the logic
(—i4V)
from IC13D with
the logic 1
(grd)
from the kedydown
buss produc-
ing a
logic 1 (grd)
output at IC13C pin
10.
Now the logic
(—14V) from IC13
pin 11
and the logic 1
(grd) from IC13
pin
10 force flip-flop
IC13A/13B to
produce
a logic 1 (grd)
at pin 3 and a
logic
(—
14V) at pin 4. The output from
pin 3 is applied to transistors
Q5
and
Q6,
and the output from pin 4 is applied
toIC12D.
With the
1678'
tab set for
the
16'
mode
(normal), J506
pin 2 of the
Bass
Generator Board
receives
—
14VDC
(logic 0). This
potential is inverted
by
ti
istor Q6.
Thus, both the
inputs of
Q6
and 1C13A
hold IC12A pin
1
to
a
logic
1 (grd) level.
(Refer to
schematic
of
Bass Generator
Board).
Also, because the
1678'
tab is set
for
16',
J506 pin
1 receives no input from
the
1678'
tab.
Therefore, transistor
Q5
becomes self biased
and produces
a
logic
1 (grd) at its
collector. This
logic
1 (grd) is
applied to pin 5 of IC12D.
Because both
IC12B pin 5 and IC12A
pin 1 are held to
logic 1 (grd) levels,
1C12B and
IC12A
pass
the inverted low
bass and medium bass
C# signals to the
envelope gates of
IC14A pin 2 and
IC14B pin 5
respectively. IC12D cannot
pass the
high bass C#
frequency to
IC14C
because IC13B is holding pin
13
of IC12D to
a logic (-14V) level.
NAND gates
IC14A and 14B cannot
pass the low and
medium hass frequen-
cies until envelope
generator
Q4
sends
logic 1 (grd) gating
pulse to their input
pins 1 and
6. The generation of the
logic
1 (grd) gating
pulse begins at the
keydown
data buss (S). When any
pedal
is depressed, a
logic 1 (grd) appears
at
the keydown
buss which is felt at
pins
12 and 13 of
NAND gate IC14D. IC14D
inverts the logic 1
(grd) to a logic
(—
14V) and sends this
level from pin 11
to the base
of transistor
Q3
(refer
to
schematic of Bass
Generator Board).
Transistor
Q3
turns on
with the
application of —14V on its
base. As
Q3
conducts,
it immediately
charges capac-
itor C3
and forces
transistor
Q4
into
conduction as
well. With
transistor
Q4
conducting,
a load is applied to
resistor
Rll which
forces the
junction of Rll
and R12to
rise from—14V to—
7V. The
—
TV is reduced
by three
560K
reristors
before heing
applied to pins 1
and 6 of IC14 sections A
and B.
Thus,
pins 2 and
6 feel logic 1
(grd) potential
as long
as the pedal remains
depressed.
As a result,
IC14A and 14B
pass the low
and
medium bass tones
into the RC
mute
filters.
When
the pedal is
released with
String Bass "OFF",
transistor Q3
shuts
off and
capacitor C3 discharges
quickly
through the
parallel
combination R9 and
RIO.
With String Bass 1 "ON",
the
capacitor discharges
through the paral-
lel combination
of R9 and RIO
in series
with a 180K
resistance.
Finally, with
Suing Bass II
"ON", the
capacitor
discharges
through the
parallel combi-
nation of R9
and RIO in series
with an
820K resistance.
The availability of these
various dis-
charge time constants
allows control
over the conduction time of
transistor
04, which in turn, controls, the
passing
of bass tones
through the envelope
gates ofIC14.
As the low
and medium bass tones
leave IC14, they
become filtered by an
RC
network before reaching the bass of
amplifier
Q10. With the mute switch in
the off
position, transistors Q8 and
Q9
receive
no
forward bias from JS06 pin 4,
and they
allow maximum signal to
transfer
from the filter to the bass of
Q10. When mute is
selected, the
transistors
receive
—
14V from pin
4;
they conduct and
shunt a portion of the
signals away
from transistor Q10.
EXAMPLE #2
-
MODE #2
Assuming that pedal #8 (G) is
depressed and the
1678'
stop is set for
16',
the following operation occurs:
Note selection
at
the data selector ICs
occurs in the same manner as example
til except:
a
priority
encoder IC3 receives the
logic 1 (grd)
keying input at its D5
pin 4.
»
data selector IC4
receives a
1, 0,
1
code at its A,
B, and C inputs
while ICs
5
and
6 are inhibited. As
a result IC4
passes the low G clock
from its X5
input
to
the Z output
buss.
IC12C receives
the low G square wave
from the Z line and
sends it to the
divider 1C15 to
form the low and
medium octaves of G.
Consequently,
the low bass is
available at pin 6 of
IC12B, the medium
bass G is available
at pin 2 of
IC12A, and the high bass G
is
available at pin 12 of IC12D.
The NAND
gates
of IC12, however,
cannot pass the
three
signals until they
receive octave
select inputs at pins 5, 1,
and 13 from
the octave
select circuitry of
IC13, 05
and Q6.
Because pedal #8 is
within the
6-13
group of pedals, the
depression of pedal
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