11. PIN DESCRIPTIONS
VA—Analog Positive Supply: Pin 34
Analog positive supply for clock generator. Nominally +2.5 V.
AGND—Analog Supply Ground: Pin 35
Analog ground for clock generator PLL.
VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23
Digital positive supplies. Nominally +2.5 V.
DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24
Digital ground.
FILT1—Phase-Locked Loop Filter: Pin 33
Connects to an external filter for the on-chip phase-locked loop.
FILT2—Phase Locked Loop Filter: Pin 32
Connects to an external filter for the on-chip phase-locked loop.
CLKIN—Master Clock Input: Pin 30
CS493XX clock input. When in internal clock mode (CLKSEL == DGND), this input is
connected to the internal PLL from which all internal clocks are derived. When in external
clock mode (CLKSEL == VD), this input is connected to the DSP clock. INPUT
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 202122 23 24 2526 27 28
6 5 4 3 2 1 4443424140
CS493XX-CL
44-pin PLCC
Top View
VD2
DATA4,EMAD4,GPIO4
VA
DATA5,EMAD5,GPIO5
DATA6,EMAD6,GPIO6
DATA7,EMAD7,GPIO7
A0, SCCLK
A1, SCDIN
RD,R/W,EMOE,GPIO11
WR,DS,EMWR,GPIO10
AUDATA3, XMT958
DGND1
VD1
SDATAN1
EXTMEM, GPIO8
ABOOT, INTREQ
SCDIO, SCDOUT,PSEL,GPIO9
CS
DATA0,EMAD0,GPIO0
DATA1,EMAD1,GPIO1
DATA2,EMAD2,GPIO2
DATA3,EMAD3,GPIO3
DGND2
RESET
DD
DC
AUDATA2
AUDATA1
AUDATA0
LRCLK
SCLK
MCLK
VD3
DGND3
SCLKN1, STCCLK2
LRCLKN1
CMPDAT, SDATAN2, RCV958
CMPCLK, SCLKN2
CMPREQ, LRCLKN2
CLKIN
CLKSEL
FILT2
FILT1
AGND
To Next Page
Loading...
