Hitachi DK23DA-20F - Page 102

K6602705
Rev.3
08.20.01
- 102 -
Figure 6-11 Device terminating an Ultra DMA Read
t
AZ
t
IORDYZ
CRC
DMARQ
(device)
DMACK-
(host)
STOP
(host)
HDMARDY-
(host)
DSTROBE
(device)
DD(15:0)
DA0, DA1, DA2,
CS0-, CS1-
t
ACK
t
LI
t
MLI
t
CVS
t
LI
t
ACK
t
ACK
t
ZAH
t
CVH
t
SS
t
LI
Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect
after DMARQ and DMACK are negated.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode3(ns) Mode4(ns) Mode5(ns) Description
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t
CVS
70 48 31 20 6.7 10 CRC word valid setup time
at sender
t
CVH
6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold time at
sender
t
LI
0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time
t
MLI
20 20 20 20 20 20 Interlock time with minimum
t
AZ
10 10 10 10 10 10 Maximum time allowed for
output drivers to release
t
ZAH
20 20 20 20 20 20 Minimum delay time for
output drivers turning on
t
IORDYZ
20 20 20 20 20 20 Maximum time before
releasing IORDY
t
ACK
20 20 20 20 20 20 Setup and hold times before
assertion and negation of
DMACK_
t
SS
50 50 50 50 50 50 Time from STROBE ed
g
e
to ne
g
ation of DMARQ or
assertion of STOP