Holtek BS82B12A-3 - Page 110

Rev. 1.20 110 January 23, 2015 Rev. 1.20 111 January 23, 2015
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
TheI
2
CfunctioncouldbeturnedofforturnedonbycontrollingthebitIICEN.Whenthepin-
sharedI/OportsarechosentobethefunctionsotherthanSDAandSCLbyclearingtheIICENbitto
zero,theI
2
Cfunctionisturnedoffanditsoperatingcurrentwillbereducedtoaminimumvalue.In
contrary,theI
2
Cfunctionisturnedonwhenthepin-sharedI/OportsarechosentobetheSDAand
SCLpinsbysettingtheIICENbithigh.
IICC1 Register
Bit 7 6 5 4 3 2 1 0
Name IICHCF IICHAAS IICHBB IICHTX IICTXAK IICSRW IICAMWU IICRXAK
R/W R R R R/W R/W R R/W R
POR 1 0 0 0 0 0 0 1
Bit7 IICHCF:I
2
CBusdatatransfercompletionag
0:Dataisbeingtransferred
1:Completionofan8-bitdatatransfer
TheIICHCFagisthedatatransferag.Thisagwillbezerowhendataisbeing
transferred.Uponcompletionofan8-bitdatatransfertheflagwillgohighandan
interruptwillbegenerated.Belowisanexampleoftheowofatwo-byteI
2
Cdata
transfer.
First,theI
2
CslavedevicereceivesastartsignalfromtheI
2
Cmasterandthenthe
IICHCFbitisautomaticallyclearedtozero.Second,theI
2
Cslavedevicefinishes
receivingthe1stdatabyteandthentheIICHCFbitisautomaticallysettoone.Third,
usersreadthe1stdatabytefromtheIICDregisterbytheapplicationprogramandthen
theIICHCFbitisautomaticallyclearedtozero.Fourth,theI
2
Cslavedevicenishes
receivingthe2nddatabyteandthentheIICHCFbitisautomaticallysethighandso
on.Finally,theI
2
CslavedevicereceivesastopsignalfromtheI
2
Cmasterandthenthe
IICHCFbitisautomaticallysethigh.
B
it6 IICHAAS:I
2
CBusaddressmatchag
0:Notaddressmatch
1:Addressmatch
TheIICHASSagistheaddressmatchag.Thisagisusedtodetermineiftheslave
deviceaddressissameasthemastertransmitaddress.Iftheaddressesmatchthenthis
bitwillbehigh,ifthereisnomatchthentheagwillbelow.
Bit5 IICHBB:I
2
CBusbusyag
0:I
2
CBusisnotbusy
1:I
2
CBusisbusy
TheIICHBBagistheI
2
Cbusyag.Thisagwillbe"1"whentheI
2
Cbusisbusy
whichwilloccurwhenaSTARTsignalisdetected.Theagwillbesetto"0"when
thebusisfreewhichwilloccurwhenaSTOPsignalisdetected.
Bit4 IICHTX:SelectI
2
Cslavedeviceistransmitterorreceiver
0:Slavedeviceisthereceiver
1:Slavedeviceisthetransmitter
Bit3 IICTXAK:I
2
CBustransmitacknowledgeag
0:Slavesendacknowledgeag
1:Slavedonotsendacknowledgeag
TheIICTXAKbitisthetransmitacknowledgeag.Aftertheslavedevicereceiptof
8-bitsofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslave
device.TheslavedevicemustalwayscleartheIICTXAKbittozerobeforefurther
dataisreceived.