Holtek BS82B12A-3 - Page 111

Rev. 1.20 110 January 23, 2015 Rev. 1.20 111 January 23, 2015
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
Bit2 IICSRW:I
2
CSlaveRead/Writeag
0:Slavedeviceshouldbeinreceivemode
1:Slavedeviceshouldbeintransmitmode
TheIICSRWflagistheI
2
CSlaveRead/Writeflag.Thisflagdetermineswhether
themasterdevicewishestotransmitorreceivedatafromtheI
2
Cbus.Whenthe
transmittedaddressandslaveaddressismatch,thatiswhentheIICHAASagisset
high,theslavedevicewillchecktheIICSRWagtodeterminewhetheritshouldbe
intransmitmodeorreceivemode.IftheIICSRWagishigh,themasterisrequesting
toreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.Whenthe
IICSRWagiszero,themasterwillwritedatatothebus,thereforetheslavedevice
shouldbeinreceivemodetoreadthisdata.
Bit1 IICAMWU:I
2
CAddressMatchControl
0:Disable
1:Enable
Iff
SYS
comesfromf
H
andisready,thenthiscontrolbitisnoeffect,I
2
Caddressmatch
canalwaysgenerateaninterruptasthisinterruptenablebitisset.
Otherwise,settingIICAMWU=1alsocangenerateaninterruptwhenI
2
Caddress
matchasthisinterruptenablebitisset,butsettingIICAMWU=0maybecan’tgenerate
aninterruptwhenI
2
Caddressmatchevenifthisinterruptenablebitisset.
Bit0 IICRXAK:I
2
CBusReceiveacknowledgeag
0:Slavereceiveacknowledgeag
1:Slavedonotreceiveacknowledgeag
TheIICRXAKagisthereceiveracknowledgeag.WhentheIICRXAKagis"0",
itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsof
datahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslave
devicecheckstheIICRXAKagtodetermineifthemasterreceiverwishestoreceive
thenextbyte.Theslavetransmitterwillthereforecontinuesendingoutdatauntilthe
IICRXAKagis"1".Whenthisoccurs,theslavetransmitterwillreleasetheSDAline
toallowthemastertosendaSTOPsignaltoreleasetheI
2
CBus.
I2CTOC Register
Bit 7 6 5 4 3 2 1 0
Name I2CTOEN I2CTOF
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 I2CTOEN:I
2
CTime-outCountrol
0:Disable
1:Enable
B
it6 IICTOF:I
2
CTime-outag
0:Notime-outoccurred
1:Time-outoccurred
Thisbitissethighwhentime-outoccursandcanonlybeclearedbyapplication
program.
B
it5~0 I2CTOS5~I2CTOS0:I
2
CTime-outperiodselection
I
2
Ctime-outclocksourceisf
SUB
/32.
I
2
Ctime-outperiodisequalto(I2CTOS[5:0]+1)×(32/f
SUB
)