Holtek BS82B12A-3 - Managing Receive� E

Rev. 1.20 128 January 23, 2015 Rev. 1.20 129 January 23, 2015
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Key 8-Bit Flash MCU with LED/LCD Driver
Receive Break
AnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.Thereceiverwill
countandexpectacertainnumberofbittimesasspeciedbythevaluesprogrammedintotheBNO
andoneSTOPSbit.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsidered
ascompleteafterthenumberofbittimesspeciedbyBNOandoneSTOPbit.TheRXIFbitisset,
FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriate
andtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceiveda
startbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRag,thereceivermustwaitfora
validstopbitbeforelookingforthenextstartbit.Thereceiverwillnotmaketheassumptionthatthe
breakconditiononthelineisthenextstartbit.Abreakisregardedasacharacterthatcontainsonly
zeroswiththeFERRagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdata
willbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyagwillgo
highwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUART
registerswillresultinthefollowing:
• Theframingerrorag,FERR,willbeset.
• Thereceivedataregister,RXR,willbecleared.
• TheOERR,NF,PERR,RIDLEorRXIFagswillpossiblybeset.
Idle Status
Whenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitand
thereadingofastopbit,thereceiverstatusagintheUSRregister,otherwiseknownastheRIDLE
ag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstart
bit,theRIDLEagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.
Receiver Interrupt
ThereadonlyreceiveinterruptagRXIFintheUSRregisterissetbyanedgegeneratedbythe
receiver.AninterruptisgeneratedifRIEbitis"1",whenawordistransferredfromtheReceive
ShiftRegister,RSR,totheReceiveDataRegister,RXR.Anoverrunerrorcanalsogeneratean
interruptifRIEis"1".
Managing Receiver Errors
SeveraltypesofreceptionerrorscanoccurwithintheUARTmodule,thefollowingsectiondescribes
thevarioustypesandhowtheyaremanagedbytheUART.
Overrun Error – OERR ag
TheRXRregisteriscomposedofatwobytedeepFIFOdatabuffer,wheretwobytescanbeheld
intheFIFOregister,whileathirdbytecancontinuetobereceived.Beforethisthirdbytehasbeen
entirelyshiftedin,thedatashouldbereadfromtheRXRregister.Ifthisisnotdone,theoverrun
erroragOERRwillbeconsequentlyindicated.
Intheeventofanoverrunerroroccurring,thefollowingwillhappen:
• TheOERRagintheUSRregisterwillbeset.
• TheRXRcontentswillnotbelost.
• Theshiftregisterwillbeoverwritten.
• AninterruptwillbegeneratediftheRIEbitisset.
TheOERRflagcanbeclearedbyanaccesstotheUSRregisterfollowedbyareadtotheRXR
register.