HP 54540 Series - Page 129

Chapter 8: Theory of Operation
Main Assembly Theory
CHX
IN > CHANNELS 2 — 4 (SAME AS CHANNEL 1)
8
out
ATTENUATOR/
-
ADC
HYBRID
ep
—
PREAMP
ADC
,
CLOCKING
,
MEMORY
if t 4 1 TO OTHER CHANNELS
CONTROL
LOW FREQ. AMP CLOCKS
CHANNEL
1
—
TRIGGER
TIME
BASE
MULTIPLEXER
AND
DRIVERS
TRIGGER QUALIFIER
eee SYCHRONIZER
TRIGGERS
FROM
eeiceee
OTHER
CHANNELS
Mu
ANO EXTERNAL
ANALOG
TRIGGER
AUX LINE
AUTO MUX
AUTO TRIG
(FROM CPU)
CINE SYNC
(FROM LINE INPUT
FILTER)
CONTROLS
TO ALL
ACQUISITION
CIRCUITRY
Acquisition Block Diagram
MHz ot
osc
REAL |25@mHz ~
Aan 32kHz
SYSTRIG
LOGIC
TRIGGER
INTERPOLATO!
PULSE
STRETCHER
TIMEBASE
HYBRID
DIVIDERS
COUNTERS
TRIGGER
INTER~
POLATOR
{7
ADDRESS DATA
TBASECLK
AC CAL [tt ee
FRONT
RT PANEL PANEL
Wy L----- PROBE
DC CAL MUX CAL
A
DIGITAL
INTERFACE
DIGITAL IN
DATA —
ANALOG
INTERFACE | contpo.
D/A CONV.
ANALOG CLOCK
>
SYSTEM
CONTROL
CPU
ROM
RAM
54542056