HP 8753D Option 011 - Page 246

Figure JUMPLOC
here.
Figure
10-2.
Jumper
P
ositions
on
the
A9
CPU
Jump
er
p
ositions
1
to
5run
right
to
left.
F
or
additional
information,
see \In
ternal T
ests"
(near
the
fron
t
of
this
section)
and
the
\Digital
Con
trol
T
roublesho
oting"
c
hapter.
5
DSP
W
r/Rd.
V
eries
the
abilit
y
of
the
main
pro
cessor
and
the
DSP
(digital
signal
pro
cessor),
b
oth on
the
A9
CPU
assem
bly
,
to
comm
unicate
with
eac
h
other
through
DRAM.
This
also
v
eries
that
programs
can
b
e
loaded
to the
DSP
,
and
that
most
of
the
main
RAM
access
circuits
op
erate
correctly
.
6 DSP
RAM. V
eries
the
A9
CPU
RAM
asso
ciated
with
the
digital
signal
pro
cessor
b
y
using
a
write/read
pattern.
7
DSP
ALU.
V
eries
the
A9 CPU
high-speed
math pro
cessing
p
ortions
of
the
digital
signal
pro
cessor.
8
DSP In
trpt.
T
ests
the
abilit
y
of
the
A9
CPU
digital
signal
pro
cessor
to
resp
ond
to
interrupts
from the
A10 digital
IF ADC.
9
DIF
Con
trol.
T
ests
the
ability
of
the
A9
CPU
main
pro
cessor
to
write/read
to
the
control
latches on the A10 digital IF.
10 DIF Coun
ter. Tests the abilit y of the A9 CPU main pro cessor to
write/read to the
triple divider on the A10 CPU. It
tests the A9 CPU data buers and A10 digital IF,
the 4 MHz clo c
k from the A12 reference.
11 DSP Con
trol. Tests the abilit
yof the A9
CPU digital signal pro cessor to write to the
control
latches on the A10 digital IF. F
eedbackisv
eried b
y the main pro cessor. It
primarily tests the A10 digital IF, but failures maybe causedbytheA9CPU.
12 FrPan Wr/Rd. Tests the ability of the A9 CPU main pro cessor to write/read to the
front panel pro cessor. It tests the A2 front panel interface and pro cessor,and A9 CPU
data buering and address deco ding. (See also tests 23 and 24 b elow.) This runs only
when selected.
DRAFT
3/21/106 15:14
Service Key Menus and Error Messages 10-7
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