System technical information
System architecture
The Integrity MC990 X system is based on a cache-coherent non-uniform memory access architecture.
Because it is modular, the Integrity MC990 X system architecture combines the advantages of lower entry
cost with the ability to scale processors, memory, and I/O independently.
The system interconnect architecture for the Integrity MC990 X system is a seventh-generation NUMAlink
SMP architecture known as NUMAlink 7. In the NUMAlink 7 architecture, all processors and memory can
be tied together into a single logical system. This combination of processors, memory, and internal
switches constitute the interconnect fabric called NUMAlink within each Integrity MC990 X system SSI.
The basic expansion building block for the NUMAlink interconnect is the MC990 X server chassis. Each
chassis uses two HARP ASICs and four Intel processors with multiple cores and on-chip secondary
caches. Each HARP ASIC supports two internal communication hubs and each of the chassis Intel
processors are connected to a hub via one 8.0GT/s quick path interconnect channel.
The HARP ASIC is the heart of the MC990 X server chassis technology. This specialized ASIC acts as a
crossbar between the processors and remote DRAM memory. The ASIC enables any processor to
access the memory of all processors in the SSI.
Figure 24: MC990 X server chassis motherboard
functional block diagram on page 66 shows a functional block diagram of the MC990 X server
chassis.
System technical information 65
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