Icom IC-756PRO - 3-3 PLL CIRCUITS

3 - 7
(2) MAIN LOOP PLL
The oscillated signal at one of the main loop VCOs (Q201,
D201, D202), (Q221, D221, D222), (Q251, D251–D254) and
(Q271, D271–D274) is amplified at the buffer amplifiers
(Q301, IC320) and is then applied to the PLL IC (IC381, pin
6). The signal is then divided and detected on phase with the
reference loop output frequency.
The detected signal output from the PLL IC (pin 2) is con-
verted into a DC voltage (lock voltage) at the loop filter and
then fed back to one of the VCO circuits (Q201, D201,
D202), (Q221, D221, D222), (Q251, D251–D254) and
(Q271, D271–D274).
The oscillated signal is amplified at the buffer amplifiers
(Q301, IC320) and then applied to the RF unit as a 1st LO A
signal after being passed through the bandpass filter (L303,
L351–L354, C304–C307, C351–C356, C358–C360).
3-3-3 2ND LO AND REFERENCE OSCILLATOR
CIRCUITS
The reference oscillator (X52, Q51) generates a 32.00056
MHz frequency for the 4 DDS circuits as a system clock and
for the LO output. The oscillated signal is doubled at the
doubler circuit (Q71, Q81) and the 64.0 MHz frequency is
picked up at the double tuned filter (L81, L82). The 64.0
MHz signal is applied to the RF unit as a 2nd LO signal.
3-3-4 3RD LO CIRCUIT
The DDS IC (IC701) generates a 10-bit digital signal using
the 32 MHz system clock. The digital signal is converted into
an analog wave signal at the D/A converter (R701–R720).
The converted analog wave is passed through the bandpass
filter (L702, L703, C709–C713) and then applied to the
MAIN unit as the 3rd LO signal.
3-3-5 MARKER CIRCUIT
The divided signal at the DDS circuit (IC101) is used for the
marker signals with the IC-756PRO.
The reference signal for the DDS circuit (32.0 MHz) is divid-
ed to produce an acceptable frequency signal, 16 MHz, with
the programmable divider then divided again by 160 to
obtain 100 kHz cycle square-wave signals.
The generated marker signals are output from pin 66 of the
DDS IC (IC101), and are then applied to the RF unit via the
mute switch (IC192) and J851 as the MKR signal.
• PLL CIRCUIT
64.485–
124.455 MHz
10.747–
10.865 MHz
64.485–
124.455 MHz
64.0 MHz
77.8 MHz
ANT
1st mixer A
Q511–Q514
491 kHz
to scope circuit (RF unit, D831) to scope circuit (RF unit, IC841)
IC801IC701
IC101
IC381
IC901
Q71
Q81
Q902
S2LOS3LO3LO2LO
1LOB
1LOA
77.8 MHz
RF unit
PLL unit
MAIN unit
Q202
Q222
Q252
Q272
Q151
1st LO PLL A
circuit
Phase
detector
1/N divider
1/22
Phase
detector
12 bit
D/A
Main loop PLL
Ref. loop PLL
DDS
1st mixer B
1st LO
PLL B
circuit
✕2
DDS
D/A
DDS
D/A
PLL
IC
Crystal
filter
2nd mixer
Q941–Q944
3rd mixer
IC151
64.455 MHz
to DSP board
Reference oscillator
X51: 32.0 MHz
BPF
Loop
filter
LPF
LPF