Infineon AN230264 - Software Execution Flow

│ │ │ ├─interrupt
│ │ │ ├─polling
│ │ │ └─reset
│ │ ├─tcpwm Basic Example of TCPWM and PWM
│ │ │ ├─capture
│ │ │ ├─counter
│ │ │ ├─pwm
│ │ │ ├─pwm_deadtime
│ │ │ ├─pwm_pseudo_random
│ │ │ └─timer
│ │ └─trigmux Basic Example of Trigger Multiplexer
│ │ ├─dma_uart_tx_rx
│ │ └─tcpwm_dma
│ ├─mw
│ │ ├─adc ADC Middleware Driver
│ │ ├─com UART configuration for ADC Middleware Driver
│ │ ├─ecc ECC Middleware Driver
│ │ ├─fbl Bootloader Middleware Driver
│ │ └─sw_uart UART based debug function Middleware Driver
│ └─system
│ ├─rev_b
│ └─rev_c
│ system_psoc4hvpa.h CMSIS Cortex-M# Device Peripheral Access
│ Layer Header File for Device <Device>
│ system_psoc4hvpa144k_cm0plus.c CMSIS Cortex-M0+ Device
│ Peripheral Access Layer Source
│ File for Device <Device>
└─tools
└─iar IAR Project Files
├─debugging
├─fbl
├─flash
└─sram
3.2.2 CPU (CM0+) startup sequence for PSoC
™
HV PA
The following steps are involved in the device startup sequence:
1. System reset (at 0x0000 0000)
2. CM0+ in SROM/boot
a. Device in privilege mode
b. Perform trimming of the device based on the 64-bit key
c. SWD initialized
d. APIs executed from Arm
®
CM0+ NMI
e. APIs for the flash program, erase, and read
f. APIs to retrieve data from privilege registers
g. Transfer control to the user program
h. Device in user mode
3. CM0+ executes the user application from the code flash region
The following steps are involved in the application startup sequence:
1. System reset (at 0x0000 0000).
Getting started with PSoC
™
HV PA family
3 Development environment and tools
Application note 12 002-30264 Rev. *B
2023-04-19