2 Feature set
PSoC
™
HV PA is a fully integrated programmable embedded system for battery monitoring and management.
The system features an Arm
®
Cortex
®
M0+ processor, and programmable and reconfigurable analog and digital
blocks.
PSoC
™
HV PA devices have these characteristics:
• High-performance, 24 to 49.152-MHz Arm
®
Cortex
®
M0+ CPU with MPU and DMA controller
• Precision analog channel subsystem (PACSS)
• High voltage subsystem (tolerant up to 42 V)
• Integrated LIN transceiver
• High-precision clock sources
• Configurable Timer Counter PWM (TCPWM) block
• Configurable Serial Communication Block (SCB) with I2C, SPI, UART, and LIN slave operating modes
• Low-power operating modes: Sleep and Deep Sleep
• Functional safety for ASIL-B according to ISO 26262
• Automotive Electronics Council (AEC) AEC-Q100 qualified
Figure 1 shows the major components of the PSoC
™
HV PA architecture.
CPU Subsystem
System Interconnect (Single Layer AHB)
PSoCһ 4 HV PA
M0S8
Architecture
IOS S G PIO
(3x
po
rt
)
I/O Subsystem
Peripheral Interconnect (MMIO)
PCLK
Flash
128KB
(+ 8 KB data flash)
Read Accelerator
(w/ECC)
SPCIF
SRAM Controller
(w/ECC)
ROM
32 KB
ROM Controller
32-bit
AHB -Lite
11x GPIOs
DeepSleep
Active/Sleep
Power Modes
Digital DFT
Test
Analog DFT
System Resources
UltraLite
Power
Clock
Reset
Clock Control
IMO
Sleep Control
REFPOR
Reset Control
TestMode Entry
WIC
XRES
WDT+ Ch/Resp
ILO
PWRSYS
4x TCPWM
LP IBS DSM
ADC (16-20+b)
x2
Precision Analog
Channel
ADC MUX
High-speed I/O Matrix
SWD/TC
NVIC, IRQMUX, MPU
Cortex® M0+
49.152 MHz
FAST MUL
SCB
-I2C/SPI/UART
SRAM
8 KB
HV SS
HV Input w/A D C
Voltage Dividers
LIN PH Y
HV Pads, ESD
HV L D O
SUPPLY MON
DataWire/
DMA
Initiator/MMIO
VDDD
V DDA
MXLIN (2x ch)
HPOSC
PILO
Peripherals
Figure 1 PSoC
™
HV PA block diagram
2.1 Function summary
• 32-bit CPU subsystem
- Up to 49.152-MHz Arm
®
Cortex
®
M0+ CPU with MPU and DMA controller
- Up to 128 KB of code flash with ECC
Getting started with PSoC
™
HV PA family
2 Feature set
Application note 4 002-30264 Rev. *B
2023-04-19
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