Code Listing 1 Sample code for CM0+ startup
;************************************************************************
;* Start-up Code
;************************************************************************
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler:
; Disable global interrupts
CPSID I
; Update Vector Table Offset Register with address of user ROM table
; (will be updated later to user RAM table address in C startup code)
LDR r0, =__vector_table
LDR r1, =VTOR
STR r0, [r1]
DSB
; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7
core
; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during
startup while SRAM ECC has not been initialized yet
; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC
SRAM
;MOVS r0, #1
;LSLS r0, r0, #19
;LDR r1, =CPUSS_RAM0_CTL0
;LDR r2, [r1]
;ORRS r2, r0
;STR r2, [r1]
;LDR r1, =CPUSS_RAM1_CTL0
;LDR r2, [r1]
;ORRS r2, r0
;STR r2, [r1]
;LDR r1, =CPUSS_RAM2_CTL0
;LDR r2, [r1]
;ORRS r2, r0
;STR r2, [r1]
; Initialize ECC of startup stack (needed for local variables in C startup code) by processing
8 bytes per loop iteration,
; because the ECC initialization feature uses this generic granularity that will cover any
memory (SRAM/TCM) in any TVII device
; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by
above code (otherwise code must be adapted)
;MOVS r0, #0 ; clear value
;MOVS r1, #0 ; clear value
;LDR r2, Cy_u32StartupStackStartAddress
startup_stack_ecc_init_loop:
;STM r2!, {r0, r1}
Getting started with PSoC
™
HV PA family
3 Development environment and tools
Application note 15 002-30264 Rev. *B
2023-04-19
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