Integra DTR-5.9 Service Manual

DTR-5.9
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-3
Q201 : D788E001BRFP266 (Floating-Point Digital Signal Processor)-3/5
TERMINAL DESCRIPTION
Pin Name
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
EM_CAS
EM_RAS
EM_WE
EM_CKE
EM_CLK
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_OE
EM_RW
Pin No.
91
89
88
86
84
83
80
79
76
75
93
74
96
94
97
100
37
98
38
71
70
39
67
104
102
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
EMIF Address Bus
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
SDRAM Chip Select
Asynchronous Memory Chip Select
SDRAM Column Address Strobe
SDRAM Row Address Strobe
SDRAM Write Enable
SDRAM Clock Enable
SDRAM Clock
Write Enable or Byte Enable for EM_D[7:0]
Write Enable or Byte Enable for EM_D[15:8]
SDRAM Output Enable
Asynchronous Memory Read/not Write
External Memory Interface (EMIF) Address and Control
External Memory Interface (EMIF) Data Bus
Pin Name
EM_D[0]
EM_D[1]
EM_D[2]
EM_D[3]
EM_D[4]
EM_D[5]
EM_D[6]
EM_D[7]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
EM_D[14]
EM_D[15]
Pin No.
52
51
49
48
46
45
43
41
66
64
63
61
59
58
56
55
Type
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Description
EMIF Data Bus [Lower 16 Bits]
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL 13942296513 QQ 376315150 892498299 TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com

Integra DTR-5.9 Specifications

General

Brand	Integra
Model	DTR-5.9
Category	Receiver
Language	English