Integra DTR-6.5 - IC Block Diagrams and Descriptions - ADV7183 A; ADV7183 AKST Functional Block Diagram; ADV7183 A Pin Configuration

DTR-6.5
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183AKST(Multiformat SDTV Video Decoder)
INPUT
MUX
DATA
PREPROCESSOR
DECIMATION AND
DOWNSAMPLING
FILTERS
A/DCLAMP
10
10
10
A/DCLAMP
10
A/DCLAMP
10
SYNC PROCESSING AND
CLOCK GENERATION
SERIAL INTERFACE
CONTROL AND VBI DATA
SC
LK
AIN1–AIN1
2
SD
A
ALS
B
CONTROL
AND DATA
SYNC AND
CLK CONTROL
CVBS
S-VIDEO
YPrPb
12
FIELD
80
OE
79
NC
78
NC
77
P16
76
P17
75
P18
74
P19
73
DVDD
72
DGND
71
NC
70
NC
69
SCLK
68
SDA
67
ALSB
66
NC
65
RESET
64
NC
63
AIN6
62
AIN12
61
VS
1
HS
2
DGND 3
DVDDIO 4
P11 5
P10 6
P9
7
P8
8
DGND 9
DVDD 10
NC 11
SFL 12
NC
13
DGND
14
DVDDIO 15
NC 16
NC 17
NC 18
P7 19
P6
20
AIN5
60
AIN11
59
AIN4 58
AIN10 57
AGND 56
CAP C2 55
CAP C1
54
AGND
53
CML 52
REFOUT 51
AVDD 50
CAP Y2 49
CAP Y1
48
AGND
47
AIN3 46
AIN9 45
AIN2 44
AIN8 43
AIN1 42
AIN7
41
P5
21
P4
22
P3
23
P2
24
NC
25
LLC2
26
LLC1
27
XTAL1
28
XTAL
29
DVDD
30
DGND
31
P1
32
P0
33
NC
34
NC
35
PWRDN
36
ELPF
37
PVDD
38
AGND
39
AGND
40
ADV7183A
TOP VIEW
(Not to Scale)
NC = NO CONNECT
80-lead LQFP pin configulation
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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