Integra DTR-8.8 - Page 154

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -88
BLOCK DIAGRAM
PIN CONFIGURATION
Q215: CDCVF2505 (Clock Driver)
TX-NR905/NA905
25 ohm
25 ohm
25 ohm
25 ohm
25 ohm
CLKOUT
8
1Y0
3
1Y1
2
1Y2
5
1Y3
7
PLL
Edge Detect
Typical < 10 MHz
Powerdown
CLKIN
1
3–State
1
2
3
4
8
7
6
5
CLKIN
1Y1
1Y0
GND
CLKOUT
1Y3
1Y2
NC
(TOP VIEW)
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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