5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
Revision A3
History
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. Intel does not warrant or represent that such use will not
infringe such rights.
Rev A1 Changes
1. Removed translator logic for PREQ0#
2. Removed termination resistors on BX side for GTL+
3. Added 20pF load on HCLK for BX clock compensating
Rev A2 Changes
HOST INTERFACE
1. Changed socket370 to socket370-256
2. Removed two 74LV07As from Host Interface page since
these signals are being pulled up to VCC_CMOS on
baseboard.
3. Removed RP1,RP2, R3,R2 pullups for CMOS signals.
4. Removed BSEL# pullup 270 ohm
5. Replaced Q1 with a MOSFET per design guide.
6. Added HRESET# termination on host interface page.
7. Added AH4 RESET pin and connected it to X4 RESET2#
8. Added 650 ohm pullup to FLUSH#
VID/Test Debug/Unused
1. Changed LC PLL component values per Aug 99 flexible
design guide
2. Added 10K RP to VID
3. Removed 330 ohm RP from VID
4. Added CMOS conversion logic for THERMTRIP#
5. Added new BSEL0#,BSEL1# circuitry
S370-256 Power
1. Removed 20 1uF bypass caps. They are on the package
for CuMine. C10-C24,C30-C34
BX Host Interface
1. Added CPURST# termination and layout guidelines
BX Memory Interface
2. Changed cap on DCLKWR to 20pf from 0.1uF. Removed
resisitor.
3. Added 10K series resistor to MAB#12 (removed from
baseboard)
Connector
1. VCC_CMOS to RESERVED16
2. Change BSEL# to BSEL0#
GTL+ Termination
1. Added new layout guidelines per flexible design
guide Aug 99
2. Added four more VTT decoupling caps to bring the
total to 20.
3. Changed 51 ohm pullup on PRDY0# to 150 ohm
Bus Ratio/Thermal/ITP
1. removed pullup on HRESET# (followed flexible design
guide)
2. move 270 ohm as a pullup for STBY# on MAX1617 per
datasheet typical operating circuit. This place cap
directly on VCC of MAX1617 per datasheet.
3. removed 10K "do not populate" resistor from STBY#.
4. removed "do not populate" for QS3257
5. added "do not populate" for RP62 0 ohm for QS3257
6. removed R48 51 ohm pullup on PRDY#
7. Added 150 ohm pullups to PRDY1#, PRDY2#, PRDY3#
8. Replaced NAND gate inverter with FET for DBRESET.
Intel(R) 440BX Scalable Performance Board
Rev A3 changes
1. Changed Q6,Q4,Q5,Q7 to Q1,Q2,Q3,Q4 respectively and
changed the MOSFET to a Fairchild FDV301N and changed the
pinout for the SOT-23 package to correct it.
2. Added a 270 ohm pull-up to PREQ# page 10
3. Corrected the ITP female socket routing. Pinout was
correct in A2, but the signals were routed incorrectly.
4. Changed silkscreen to read "Flexible Intel(R) 440BX
AGPset/PGA370 Processor adapter"
5. Page 3: Silkscreen pin numbers for Socket-370 on TOP
and BOTTOM layers.
6. Changed R6,R7 to 270 ohms
7. Made C1 a Don’t Pop.
8. Changed all Don’t Pops to have EMPTY as their value.
this way they sort together when generating BOM.
9. Page 6, BX. Removed R16,R17,R18. Added silkscreen
pin numbering for BX. Added four testpoints to ground
under BX. Placed tuning caps C86,87,88 within 1/2 inch
of BX.
10. Page 10. Changed 3.3V power to QS3257 to 5.0V.
Changed R40 from 3.3K to 270 ohm.
11. BSEL0 pulled to 3.3V. (it was pulled to 2.5V).
12. R105 changed from 680 ohms to 280 ohms.
13. HCLK0,HCLK1 routing changed. These two signals must
be on same layer, bottom layer, and not traverse multiple
layers.
14. Also, on connector, pin K33, HCLK0 and pin K35,
HCLK1 have been swapped. Now, in rev A3, HCLK0 is K35,
and HCLK1 is K33. This is to accomodate routing these
two signals on the same (bottom) layer. Otherwise, they
would have criss-crossed. This has no effect on the
circuit since the clocks are tied together on baseboard.
15. The three AGTL+ test signals BNR#,HD4#,HA27# had a
min. of 1.6", this has been changed to a min. of 1.8".
16. Page 9. The AGTL+ signals min. has been changed to
1.8" (used to be 1.6").
A3
Intel(R) 440BX Scalable Performance Board
Embedded Intel Architecture Division
Intel Corporation
5000 W. Chandler Blvd
Chandler AZ, 85044
C
112Wednesday, April 26, 2000
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