Beep Codes, Error Messages, and POST Codes
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4.3 Port 80h Power On Self Test (POST) Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O
port 80h. If the POST fails, execution stops and the last POST code generated is left
at port 80h. This code is useful for determining the point where an error occurred.
Displaying the POST codes requires a PCI bus add-in card, often called a POST card.
The POST card can decode the port and display the contents on a medium such as a
seven-segment display.
NOTE
In order to view POST codes on a diagnostic card inserted into a PCI slot, the BIOS
must be enabled to route POST codes to the PCI slots. The default setting is to route
them to the LPC debug header, as this is required to pass Windows 8 certification.
The following tables provide information about the POST codes generated by the BIOS:
Table 46 lists the Port 80h POST code ranges
Table 47 lists the Port 80h POST codes themselves
Table 48 lists the Port 80h POST sequence
NOTE
In the tables listed above, all POST codes and range values are listed in hexadecimal.
Table 46. Port 80h POST Code Ranges
Entering SX states S0 to S5.
0x10, 0x20, 0x30,
Resuming from SX states. 0x10 – S1, 0x20 – S2, 0x30 – S3, etc.
PEI phase pre MRC execution
PEI phase post MRC execution
CPU Initialization (PEI, DXE, SMM)
I/O Buses: PCI, USB, ISA, ATA etc. 0x5F is an unrecoverable error. Start with PCI.
Output Devices: All output consoles.
Input devices: Keyboard/Mouse.
0xB0 – 0xBF Boot Devices: Includes fixed media and removable media. Not that critical since
consoles should be up at this point.
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