Date Version Changes
May 2016 2016.05.02 • Removed all preliminary marks.
• Update the ADC sampling rate description. The ADC feature monitors
single-ended external inputs with a cumulative sampling rate of 25
kilosamples per second to 1 MSPS in normal mode.
November 2015 2015.11.02 • Removed SF feature from the device ordering information figure.
• Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 • Added clearer descriptions for the feature options listed in the device
ordering information figure.
• Updated the maximum dedicated LVDS transmitter count of 10M02
device from 10 to 9.
• Removed the F672 package of the MAX 10 10M25 device :
— Updated the devices I/O resources per package.
— Updated the I/O vertical migration support.
— Updated the ADC vertical migration support.
• Updated the maximum resources for 10M25 device:
— Maximum GPIO from 380 to 360.
— Maximum dedicated LVDS transmitter from 26 to 24.
— Maximum emulated LVDS transmitter from 181 to 171.
— Maximum dedicated LVDS receiver from 181 to 171.
• Added ADC information for the E144 package of the 10M04 device.
• Updated the ADC vertical migration diagram to clarify that there are
single ADC devices with eight and 16 dual function pins.
• Removed the note about contacting Altera for DDR3, DDR3L, DDR2,
and LPDDR2 external memory interface support. The Quartus Prime
software supports these external memory interfaces from version 15.0.
December 2014 2014.12.15 • Changed terms:
— "dual image" to "dual configuration image"
— "dual-image configuration" to dual configuration"
• Added memory initialization feature for Flash and Analog devices.
• Added maximum data retention capacity of up to 20 years for UFM
feature.
• Added maximum operating frequency of 7.25 MHz for serial interface
for UFM feature.
September 2014 2014.09.22 Initial release.
1 MAX
®
10 FPGA Device Overview
MAX 10 FPGA Device Overview
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