JVC RC-BM5 Service Manual

RC-BM5
1-22
SAA7324 (IC501) : Digital servo processor & compact disc decoder
1. Terminal layout
2. Block diagram
ADC
PRE.
PROCESSING
CONTROL
FUNCTION
Vref
GENERATOR
MICROCONTROLLER
INTERFACE
CONTROL
PART
FRONT-
END
DIGITAL
PLL
EFM
DEMODULATOR
MOTOR
CONTROL
TEST
TIMING
SRAM
RAM
ADDRESSER
SUBCODE
PROCESSOR
DECODER
MICRO-
CONTROLLER
INTERFACE
VERSATILE PINS
INTERFACE
BITSTREAM
DAC
SERIAL DATA
(LOOPBACK)
INTERFACE
SERIAL DATA
INTERFACE
EBU
INTERFACE
AUDIO
PROCESSOR
VSSA1
D1 D2 D3 D4
8 91011
V
SSA2
V
DDA1
V
DDA2
V
SSD1
V
SSD2
V
SSD3
V
DDD1(P)
VDDD2(C)
4 14 5 17 33 50 58 52 57
12
13
R1
R2
OUTPUT
STAGES
7
VRIN
SCL
SDA
RAB
SILD
40
39
HFIN
HFREF
ISLICE
Iref
2
1
3
6
TEST1
TEST2
TEST3
25
31
44
SELPLL
CRIN
CROUT
CL16
CL11/4
24
16
15
26
49
48
47
46
45
SBSY
SFSY
SUB
RCK
43
STATUS
RESET
38
63 34 61 62
V1 V2/V3 V4 V5 KILL
32
KILL
PEAK
DETECT
23
22
19
18
21
20
RP
RN
LP
LN
VPOS
Vneg
36
35
37
SDI
WCLI
SCLI
30
29
28
27
EF
SCLK
WCLK
DATA
DOBM
51
ERROR
CORRECTOR
FLAGS
53
CFLG
59
60
MOTO1
MOTO2
64
LDON
56
55
54
SL
FO
RA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 21 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SAA7324H
HFREF
HFIN
ISLICE
V
SSA1
V
DDA1
I
ref
V
RIN
D1
D2
D3
D4
R1
R2
V
SSA2
CROUT
CRIN
V
DDA2
LN
LP
V
neg
V
pos
RN
RP
SELPLL
TEST1
CL16
DATA
WCLK
SCLK
EF
TEST2
KILL
SBSY
SFSY
SUB
RCK
TEST3
STATUS
SILD
RAB
SCL
SDA
RESET
SCLI
SDI
WCLI
V2/V3
V
SSD1
LDON V1 V5 V4 MOTO2 MOTO1 V
SSD3
V
DDD2(C)
SL FO RA CFLG V
DD1(P)
DOBM V
SSD2
CL11/4
41
42
Description of major ICs

JVC RC-BM5 Specifications

General

Brand	JVC
Model	RC-BM5
Category	CD Player
Language	English