Keithley 2290-5 - Status Byte Register; Standard Event Status Register

Section
5: Status messages Model 2290-5 5 kV Power Supply
User's Manual
5-2 2290-5-900-01 Rev. A/December 2013
Status byte register
The next table summarizes bits in the Status Byte, which may be read with the *STB? query or with
the serial polling sequence. The Model 2290-5 will generate a service request (SRQ) whenever one
of these bits is set and the corresponding bit in the Service Request Enable Register is set, except for
bit 6, the RQS/MSS bit. (Use the *SRE command and the decimal bit value in the table to set Service
Request Enable Register bits.) Note that any given status condition will produce only one SRQ even if
that condition is never cleared.
Table: Status byte
Bit Decimal
value
Name Description
0 1 Stable
Indicates that the VSET or ILIM value is stable. The function depends on whether the
Model 2290-5 is in current limit or constant voltage mode.
1
2
1
V trip
Indicates that a voltage trip has occurred.
2
4
1
I trip
Indicates that a current trip has occurred.
3
8
1
I lim
Indicates that a current limit condition has occurred.
4
16
MAV
Indicates message available in the GPIB output queue.
5
32
ESB
Indicates that an unmasked bit in the Standard Event Status Register has been set.
6
64
2
RQS/MSS
Request for Service/Master Summary Status.
7 128 HV on Indicates that the high voltage is on.
Note: SRQ may be enabled for corresponding condition by sending *SRE with decimal value of bit (except bit 6). For
example, *SRE 4 enables SRQ on current trip.
1
The V trip, I trip, and I lim bits are latched bits. They are set on the occurrence of the appropriate event and will remain set
until either the status byte is read or the *CLS command is sent. Latching allows you to detect if a trip or limit condition has
ever occurred.
2
Request for Service bit in serial poll byte. Master Summary Status bit in *STB? response.
Standard event status register
The next table summarizes the bits in the Standard Event Status Register, which can be read using
the *ESR? query. This status register is defined by the IEEE-488.2 standard and is used primarily to
report errors in commands received over the GPIB. When the bits in this register are latched, they
stay latched and are cleared by reading them, or by sending the *CLS command. If a bit in the
Standard Event Status Register is latched and the corresponding bit in the Standard Event Status
Enable Register (programmed with *ESE) is also latched, the ESB bit in the Status Byte Register is
latched.