LeCroy WAVERUNNER 6000 SERIES - Page 4

ii Table of Contents
Theory of Operation
System Block Diagram 4-1
4.2 Computer 4-2
4.2.1 Operating System 4-2
4.2.2 Memory 4-2
4.2.3 Interfaces 4-2
4.2.4 Storage Devices 4-2
4.2.5 CMOS Settings 4-2
4.3 PCI Card 4-3
4.4 USB Hub 4-3
4.5 Display and Touch Screen 4-4
4.5.1 Color LCD Module 4-4
4.5.2 Inverter 4-4
4.5.3 Touch Screen 4-4
4.6 Acquisition System 4-5
4.6.1 Main Card 4-6
4.6.1.1 JTAG Chains 4-7
4.6.1.2 Serial chains 4-7
4.6.1.3 Controller FPGA 4-8
4.6.1.4 MicroController 4-8
4.6.1.5 Timebase & Trigger 4-9
4.6.1.5.1 HTB645 4-9
4.6.1.5.1.1 Trigger Bandwidth 4-9
4.6.1.5.1.2 Trigger Signal I/O 4-10
4.6.1.5.1.3 TDC 4-10
4.6.1.5.1.4 Timebase 4-10
4.6.1.5.1.5 Miscellaneous clocks 4-10
4.6.1.5.2 MST429A – Smart Trigger IC 4-10
4.6.1.5.2.1 Signal I/O 4-10
4.6.1.5.2.2 Trigger Functions 4-10
4.6.1.5.2.3 Main trigger delay 4-10
4.6.1.5.2.4 Qualifier selection 4-10
4.6.1.5.2.5 Polarity 4-10
4.6.1.5.2.6 Analog Time Measure 4-10
4.6.1.5.2.7 Digital Time Measure 4-10
4.6.1.5.2.8 Trigger Frequency 4-11
4.6.2 ADC & Memory 4-11
4.6.2.1 HAD639 4-11
4.6.2.1.1 Signal I/O 4-11
4.6.2.1.2 ADC’s 4-11
4.6.2.1.3 Calibration 4-11
4.6.2.1.4 Control 4-11
4.6.2.2 MAM439 4-12
4.6.2.2.1 Signal I/O 4-12
4.6.2.2.2 Control 4-12
4.6.2.2.3 Decimation 4-12
4.6.2.3 8b/10b Bus 4-12
4.6.3 Front End 4-13