LeCroy WAVERUNNER 6000 SERIES - Page 5

4.6.3.1 Input Coupling 4-13
4.6.3.2 50Ω Path 4-13
4.6.3.3 1MΩ Path 4-14
4.6.3.4 HFE653 4-14
4.6.3.5 Amplifier Signal Path 4-15
4.6.3.5.1 Power Off State 4-15
4.6.3.5.2 50Ω /1 Path 4-16
4.6.3.5.3 50Ω /10 Path 4-16
4.6.3.5.4 1MΩ /1 Path DC Coupled 4-17
4.6.3.5.5 1MΩ /10 Path DC Coupled 4-17
4.6.3.5.6 1MΩ /100 Path DC Coupled 4-18
4.6.3.5.7 1MΩ /1 Path AC Coupled 4-18
4.6.4 Other Sub Systems 4-19
4.6.4.1 Power Supply 4-19
4.6.4.2 NCO (Numerically Controlled Osc.) 4-19
4.6.4.3 10GHz Clock 4-19
Theory of Operation - List of Figures
Figure 4-1 WaveRunner 6000 Block Diagram 4-1
Figure 4-2 Device Manage 4-3
Figure 4-3 Acquisition Main Board Block Diagram 4-5
Figure 4-4 JTGA Device Chains 4-7
Figure 4-5 Serial Bus Device Chains 4-8
Figure 4-6 Trigger and Timebase Block Diagram 4-9
Figure 4-7 ADC and Memory Block Diagram 4-11
Figure 4-8 8b/10b Path 4-12
Figure 4-9 Front End Card Block Diagram 4-13
Figure 4-11 Front End Power Off State Block Diagram 4-15
Figure 4-10: HFE653 Block Diagram 4-15
Figure 4-12 50Ω /1 Path Block Diagram 4-16
Figure 4-13 50Ω /10 Path Block Diagram 4-16
Figure 4-14 1MΩ /1 Path DC Coupled Block Diagram 4-17
Figure 4-15 1MΩ /20 Path DC Coupled Block Diagram 4-17
Figure 4-16 1MΩ /20 Path DC Coupled Block Diagram 4-18
Figure 4-17 1MΩ /1 Path AC Coupled Block Diagram 4-18
Figure 4-18 Cal Clock Block Diagram 4-19
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