Interrupt Controller
In order to prioritize and control several interrupt sources, it is necessary to use an
IC of uPD71059. It scans eight interrupt signals and sends a unique interrupt signal
to the processor when an (unmasked) interrupt signal appears.
Interrupt levels are assigned as follows:
level 0 (lowest priority) FDC
level 1 small peripherals
level 2 RS232C
level 3 GP-IB
level 4 PCMCIA (I/O card mode)
level 5 real time clock
level 6 the MAIN board
level 7 (highest priority) unused
The priority in the above can be changed by the software.
Small Peripheral Interface
This 8-bit interface is intended to allow external expansion of the board in addition to
the processor board. The tri-state buffers drive the address and control lines, and
bi-directional buffers drive data lines. The address decoding is processed on each
expanded peripheral board. Since the acknowledgement toward each access is
also returned by the expanded board, there is no restriction to the amount of wait-
states. The bus clock runs at 16MHz, and a reset line reinitializes the boards as
does the CPU. Four interrupt lines are also included in this interface, so that
interrupt-driven boards can be used.
Front Panel
The front panel is accessed by serial read/write signals passing through IC47 and
IC48. The CPU board can be reset by resetting the 3 buttons on the front panel.
This function becomes effective by setting a bit of IC52 for enabling. Both the LED
and the beeper are activated by serial writing.
Reset Circuit
When the power supply is turned on and V
CC
exceeds 4.5V, IC4 detects this and
starts generating the clock (IC2) After the clock is stabilized and counted 1024
times, the reset signal is released by IC86 after the time determined by C167.
Whenever V
CC
goes below 4.5V (even for a very short time), a reset pulse, in which
the width is determined by C6, is generated. Resetting 3 buttons on the front panel
also cause the reset pulse as did IC4 when the supply power voltage fell too low.
Theory of Operation 4-7
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