MPX G2 Service Manual
6-10
bit 3 RESET_UART. When 1, resets the MIDI UART. This needs to be set for at least 1 usec after
power-up.
bit 4 ENABLE_BUSREQ. Gates DEG0. When 1, allows DSP_ON_BUS to go high after DEG0. When
0, keeps DSP_ON_BUS at 0.
bit 5 SELECT_FOOT. Determines whether the footpedal or the front panel pots will be converted by the
DSP's integrating ADC. When 1, the footpedal is selected. When 0, one of the pots is selected.
Bit 5 is new to MPX G2.
REGISTER 2 WRITE:
bit 0 undefined
bit 1 undefined
bit 2 undefined
bit 3 RESET_COUNTER. When 1, resets the word clock counter, turning off FC and its multiples. The
Z80 sets RESET_COUNTER to resync the 2186.
bit 4 undefined
bit 5 undefined
bit 6 undefined
bit 7 undefined
The DSP performs a write to register 2 in order to relinquish the bus.
REGISTER 2 READ
bit 0 UART TXRDY. UART transmit ready. 0 = busy. The processor must not write to the UART when
this line is low. A write to the UART will set TXRDY within 1 usec.
bi 1 RXRDY. UART receive ready. 1 = receive data is ready. Reading from the UART address clears
this bit.. On power-up, the Z80 should read the UART address to pre-clear RXRDY.
bit 2 FRAMING ERROR. When set, indicates a UART receive framing error. This bit is updated every
time a serial byte is received in the UART. It is not valid unless the RXRDY bit is also set.
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