Lexicon
6-11
I/O Map
To reduce the load on the system data bus, the I/O bus is isolated from the main bus with a transceiver
(see Sheet 4 description under Schematic Walk-through). The direction of the transceiver is controlled by
the A0 line. Thus, all odd I/O addresses must be writes and all even addresses must be reads.
A7 A6 A5 A4 READ WRITE
------------------------------------------------------------------------------------------------------------------
0 0 0 0 STATUS 1 CONTROL_WR
0 0 0 1 STATUS 2
0 0 1 0 BLUE_WR1
0 0 1 1
0 1 0 0 DISPLAY_WR1
0 1 0 1
0 1 1 0 DISPLAY_WR2
0 1 1 1
1 0 0 0 LCD_CTL_WR
1 0 0 1 SPEAKER
1 0 1 0 BLUE_WR2
1 0 1 1
1 1 0 0 LCD LCD
1 1 0 1
1 1 1 0 (BLUE_WR3)
1 1 1 1
STATUS 1 ( U71, U75, sheet 5):
BIT 0 SWITCH_ROW 0
BIT 1 SWITCH_ROW 1
BIT 2 SWITCH_ROW 2
BIT 3 SWITCH_ROW 3
BIT 4 DIGIPOT_FPK: serial output from the digipot chain, used for diagnostic feedback
STATUS 2 (U71, U75, sheet 5):
BIT 0 ENC1 (phase A of the rotary encoder)
BIT 1 ENC2 (phase B of the rotary encoder)
BIT 2 footswitch tip
BIT 3 footswitch ring
BIT 4 LEFT_INSERT_STAT: 0 = plug inserted into left return
BIT 5 RIGHT_INSERT_STAT: 0 = plug inserted into right return
CONTROL (U66, sheet 4):
This is an addressable latch. A1 determines whether a bit is set or reset, and A2-A4 determines the bit to
change.
ADDRESS
01, 03 _RESET_DSP resets the 2186 when low.
04, 07 _MUTE mutes the analog outputs when low.
09, 0B _RESET_LEX resets the lexichip when low.
0D, 0F AUX_MONO_SUM sums the right Aux input to the left when high
11, 13 SPEAKER_SIM_FREQ_A
15, 17 SPEAKER_SIM_FREQ_B
; old11, 13 SOFT_SAT enables soft saturation of the ADC when high.
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