MPX G2 Service Manual
6-12
; old15, 17 _RESET_ADC resets the ADC when low (new for MPX G2)
19, 1B _RESET_DAC resets the DAC when low
1D,1F MIX_INSERT (new for MPX G2)
These signals are initialized to 0 by _RESET.
DISPLAY 1 (U74, sheet 3):
bit 0 column address 0
bit 1 column address 1
bit 2 column address 2
bit 3 RIGHT_ROW0
bit 4 RIGHT_ROW1
bit 5 RIGHT_ROW2
bit 6 RIGHT_ROW3
These signals are initialized to 0 by _RESET1. There are five columns of LED's, starting at address 1 and
ending at address 6. Address 0 is unused. The RIGHT_ROW bits are active high, unlike the left row bits.
DISPLAY 2 (U63, sheet 3):
bit 0 left row 0
bit 1 left row 1
bit 2 left row 2
bit 3 left row 3
bit 4 left row 4
bit 5 left row 5
bit 6 left row 6
bit 7 left row 7
These bits are active low.
LCD CONTROL (U72, sheet 3):
bit 0 CONTRAST0
bit 1 CONTRAST1
bit 2 CONTRAST2
bit 3 CONTRAST3
bit 4 LCD_READ
bit 5 LCD_ADDR1
bit 6 SOFT_SAT
bit 7 (unused)
These signals are described in sheet 3 of the schematic walkthrough.
SPEAKER
Note: The speaker simulator freq is not used in REV2 and up.
The FPGA contains a programmable 8-bit counter, whose output, SPEAKER_FREQ, drives the switched-
capacitor speaker simulator filter. SPEAKER_FREQ is a square wave whose frequency is 100 times the
cutoff frequency of the filter. The counter should be programmed to: 256 - (225792/Fc) where Fc is the
cutoff frequency in Hz. The lowest cutoff frequency is 882 Hz. In the 3KHz - 7KHz range, changing the
modulus by 1 changes the fc by less than two semitones.
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